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| Preliminary HD66781 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM REJxxxxxxx-xxxxZ Rev.0.5 July.31.2003 * Index Description ......................................................................................................... 6 Features ......................................................................................................... 7 Block Diagram .................................................................................................... 8 Pin Functions ...................................................................................................... 9 HD66781 power-supply specification.................................................................................... 14 Pad Arrangement................................................................................................. 15 Pad Coordinate.................................................................................................... 16 Bump Arrangement............................................................................................. 18 Example of Connecting HD66781 and HD66783 .............................................. 19 Example of Connecting HD66781 and HD667P21 ............................................ 20 Block Function.................................................................................................... 21 (1) System interface................................................................................................................ 21 (2) External Display Interface (RGB I/F, VSYNC I/F).......................................................... 22 (3) Address Counter (AC) ...................................................................................................... 22 (4) Graphic RAM (GRAM).................................................................................................... 22 (5) Grayscale Voltage Generation Circuit .............................................................................. 22 (6) Timing generator............................................................................................................... 23 (7) Oscillation Circuit (OSC) ................................................................................................. 23 (8) Liquid Crystal Display Driver Circuit .............................................................................. 23 (9) Gate driver/power supply IC interfacing circuit ............................................................... 23 GRAM Address MAP......................................................................................... 24 Relation between GRAM addresses and Screen positions (SS=0, BGR=0) .......................... 24 Relation between GRAM data and Display data (SS=0, BGR=0)......................................... 25 Relation between GRAM address and Screen position (SS=1, BGR=1)............................... 28 Relation between GRAM data and Display data (SS=1, BGR=1)......................................... 29 Rev. 0.5, July.31.2003, page 1 of 196 HD66781 Preliminary Instruction ......................................................................................................... 32 Outline ................................................................................................................................... 32 Instruction data format ........................................................................................................... 33 Basic Operation modes ....................................................................................... 34 Index/Status/Display control instruction................................................................................ 35 Index (IR)............................................................................................................................... 35 Status read (SR) ..................................................................................................................... 35 Start Oscillation (R000h) ....................................................................................................... 35 Driver Output Control (R001h).............................................................................................. 36 LCD Driving Wave Control (R002h) .................................................................................... 36 Entry Mode 1 (R003h) ........................................................................................................... 37 Resizing Control 1/2 (R004/R005h) ...................................................................................... 42 Display Control 1 (R007h)..................................................................................................... 44 Display Control 2 (R008h)..................................................................................................... 46 Display Control 3 (R009h)..................................................................................................... 47 Display Control 4 (R00Bh) .................................................................................................... 49 External Display interface Control 1 (R00Ch)....................................................................... 51 Frame Cycle Control (R00Dh)............................................................................................... 54 External Display Interface Control 2 (R00Eh)....................................................................... 55 External Display Interface Control 3 (R00Fh)....................................................................... 55 Gate Driver/LTPS LCD Panel Interface Control 1 (R010h).................................................. 56 Gate Driver/LTPS LCD Panel Interface Control 2 (R011h).................................................. 57 Gate Driver/LTPS LCD Panel Interface Control 3 (R012h).................................................. 58 Gate Driver/LTPS LCD Panel Interface Control 4 (R013h).................................................. 59 Gate Driver/LTPS LCD Panel Interface Control 5 (R015h).................................................. 60 Gate Driver/LTPS LCD Panel Interface Control 6 (R016h).................................................. 61 Gate Driver/LTPS LCD Panel Interface Control 7 (R017h).................................................. 62 Gate Driver/LTPS LCD Panel Interface Control 8 (R018h).................................................. 63 Gate Driver/LTPS LCD Panel Interface Control 9 (R019h).................................................. 64 Gate Driver/LTPS LCD Panel Interface Control 10 (R01Bh) ............................................... 65 Power control 1 (R100h)........................................................................................................ 68 Gate Driver/ Power Supply IC Interface Control 1 (R110h).................................................. 70 Gate Driver/ Power Supply IC Interface Control 2 (R111h).................................................. 70 Setting examples .................................................................................................................... 72 Common registers for HD66783 and HD667P21 .................................................................. 73 Registers of HD66783............................................................................................................ 73 Registers of HD667P21 ......................................................................................................... 74 RAM Address set in horizontal/vertical directions (R200h/R201h) ...................................... 76 RAM Access through RGB-I/F and System I/F..................................................................... 86 RAM Write Data Mask 1/2 (R203h/R204h) .......................................................................... 89 Window Address Control Instructions................................................................................... 90 Control (R300h ~ R309h).................................................................................................... 91 Base image display control instructions................................................................................. 92 Instruction list ..................................................................................................... 96 Reset Function .................................................................................................... 98 Rev.0.5, July.31.2003, page 2 of 196 HD66781 Preliminary RAM Address and Display Position on the Panel .............................................. 99 Notes to the setting of panel control registers ........................................................................ 100 Screen settings ....................................................................................................................... 100 Base image display ................................................................................................................ 100 OSD and blending functions ........................................................................... 102 OSD image data format.......................................................................................................... 103 OSD image display setting..................................................................................................... 103 Resizing function ................................................................................................ 105 Contraction............................................................................................................................. 105 Resizing setting...................................................................................................................... 106 Instructions for Resizing ........................................................................................................ 107 Notes to the resizing function ................................................................................................ 108 Magnification......................................................................................................................... 109 Interface specification ......................................................................................... 112 System Interface.................................................................................................. 114 80-system 18-bit interface...................................................................................................... 115 80-system 16-bit interface...................................................................................................... 116 Data transmission synchronization in 16-bit bus interface mode........................................... 118 80-system 9-bit interface........................................................................................................ 119 Data transmission synchronization in 9-bit bus interface mode............................................. 120 80-system 8-bit interface (Big endian)................................................................................... 121 Data transmission synchronization in 8-bit bus interface mode............................................. 124 Serial Peripheral interface (SPI) ............................................................................................ 125 80-system 8-bit interface (Little endian)................................................................................ 128 Data transmission synchronization in 8-bit bus interface mode............................................. 130 DMA transfer Single Address mode ................................................................... 131 VSYNC Interface................................................................................................ 134 Notes to the VSYNC interface............................................................................................... 137 External Display Interface .................................................................................. 139 Polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals .............................................. 140 RGB interface timing ............................................................................................................. 140 Moving picture display in RGB Interface .............................................................................. 142 RAM access through the system interface in RGB-I/F mode ................................................ 142 6-bit RGB interface................................................................................................................ 143 Transfer synchronization function for a 6-bit bus interface ................................................... 144 16-bit RGB interface.............................................................................................................. 145 18-bit RGB interface.............................................................................................................. 146 Notes to the external display interface ................................................................................... 147 Display Synchroniaing Data Transfer................................................................. 148 Notes to the display synchronizing GRAM data transfer mode............................................. 150 Rev.0.5, July.31.2003, page 3 of 196 HD66781 Preliminary Timing interfacing with LCD panel signals........................................................ 151 High-Speed Burst RAM Write Function ............................................................ 153 Notes to the high-speed RAM write mode............................................................................. 154 High-Speed RAM Write with Window Address Function..................................................... 155 Window Address Function ................................................................................. 156 -Correction Function ......................................................................................... 157 Grayscale Amplifier Configuration........................................................................................ 158 -Correction Registers............................................................................................................ 160 Ladder resistors and 8 to 1 selector........................................................................................ 162 Variable resistors ................................................................................................................... 162 Relationship between RAM data and output level (REV =0) ................................................ 167 Relationship between RAM data and output level (REV =1) ................................................ 168 Low Power Consumption Display Mode............................................................ 169 8-color Display Mode ......................................................................................... 172 Oscillation Circuit............................................................................................... 173 n-raster-row Inversion alternating Drive ............................................................ 174 Interlaced Drive .................................................................................................. 175 Alternating Timing.............................................................................................. 177 Frame-Frequency Adjustment Function ............................................................. 178 Relationship between Liquid Crystal Drive Duty and Frame Frequency .............................. 178 Partial Display Function ..................................................................................... 179 Power-saving drive settings ................................................................................ 180 Equalization function .......................................................................................... 183 Specifications of external element of HD66781 ................................................. 184 Instruction Setting............................................................................................... 185 Power-supply/display ON (LPTS = 0: a-Si TFT panel, with HD66783) ............................... 186 Power-supply/display OFF (LPTS = 0: a-Si TFT panel, with HD66783) ............................. 187 Power-supply/display ON (LPTS = 1: LTPS TFT panel, with HD667P21).......................... 188 Power-supply/display OFF (LPTS = 1: LPTS TFT panel, with HD667P21) ........................ 189 Standby/Sleep mode............................................................................................................... 190 Deep standby mode................................................................................................................ 191 Low power consumption display mode.................................................................................. 192 8-color mode .......................................................................................................................... 192 Rev.0.5, July.31.2003, page 4 of 196 HD66781 Preliminary Partial display mode............................................................................................................... 193 Absolute Maximum Values ................................................................................ 194 Rev.0.5, July.31.2003, page 5 of 196 HD66781 Preliminary Description The HD66781 is a 720-channel source driver with graphics acceleration function, incorporating RAM compliant to 262,144 TFT colors and 240RGB x 320 dot graphics. In combination with the HD66783, which incorporates a power-supply integrated circuit and a gate driver on a single chip, the HD66781 can drive an a-Si TFT panel of 240 RGB x 320 dots at maximum. Also in combination with the HD667P21, which is a power-supply IC chip, the HD66781 can drive a low-temperature poly-Si TFT panel of 240 RGB x 320 dots at maximum with an incorporated gate driver. The HD66781's high-speed RAM-write function through a high-speed interface of 8/9/16/18-bit bus enables efficient data transfer with high-speed burst RAM write function. The HD66781 is compliant to DMA transfer single address mode to keep control on bus traffic occupation when a large volume of data is transferred from external memory. The HD66781 can also handle moving picture display through an RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0). The HD66781 incorporates RAM with the capacity of one QVGA-sized whole screen of 240 RGB x 320 x 18bits plus 96 raster-rows. In addition to OSD and blending functions, which use this RAM area, the HD66781 also handles resizing function, which is compliant to data transfer for a large screen display. These functions make the HD66781 the best solution for the efficient and various ways of display. The combined use of HD66781 with HD66783 or HD667P21 supports the function to reduce power consumption by a liquid crystal display system. The HD66781's RAM can display 240 RGB x 320-dot color display (max.) with low voltage operation up to 1.7 V. The HD66781 incorporates a voltage follower circuit to generate liquid crystal driving voltages and an interfacing circuit that enables through HD66781 to make instruction settings to HD66783 and HD667P21. In addition, the HD66781 supports power-saving modes such as standby mode and 8-color display mode, which allow precise power management by software. These features make this LSI the ideal solution for medium or small-sized portable batterydriven products such as digital cellular phones or small PDA with color displays, where long battery life and board size are a major concern. Rev.0.5, July.31.2003, page 6 of 196 HD66781 Preliminary Features * * * * Drive 262,144 TFT-color 240RGB x 320 dot graphics display in combination with HD66783 (a-Si TFT panel) or HD667P21 (low-temperature poly-Si TFT panel) Output signals to control HD66783, which incorporates a power supply integrated circuit and a gate driver on a single chip. Output signals to control a low-temperature poly-Si TFT panel with an incorporated gate driver (combined use with HD667P21) System interface - High-speed bus interface with 8-/9-/16-/18-bit data bus - Serial Peripheral Interface (SPI) Interfaces for moving picture display - RGB interface with 6-/16-/18-bit data bus (VSYNC, HSYNC, DOTCLK, ENABLE, PD17-0) - VSYNC interface (System interface + VSYNC) High-speed burst RAM write function Compliant to single address mode for DMA transfer that controls data bus occupation ratio when transferring data from external SRAM Window address function to write data to a rectangular area of RAM specified by the window address - Interfaces for moving picture display, which write data to a rectangular RAM address area - Reduce data transfer by transferring only the data for the moving picture display area - Simultaneous display of moving picture area and still picture area that displays the contents of internal RAM - Resizing function (contraction rate: x1/2, x1/4 / magnification rate: x2, x4) Various functions to control color display - Simultaneous availability of 262,144 colors (settings are programmable) - Partial OSD function - -blending function (transmission rate: 0%, 25%, 50%, 75%, 100%) Features for low-power architecture - Interface I/O power supply - - - - - * * * * IOVcc = 1.7 ~ 3.3 V Vcc1 = 1.7 ~ 3.3 V Logic regulator power supply Vcc = 2.5 ~ 3.3 V Source driver liquid crystal driving voltage DDVDH-GND = 4.0 ~ 5.9 V Power saving functions: standby mode, deep standby mode etc. Step-up circuits to generate liquid crystal drive voltage up to 12 times (HD66783 and HD667P21) Voltage followers for a liquid crystal drive power-supply, which fends off the direct current from bleeder-resistors * * * * * * Cst structure only (Common Vcom formula) 224,640-byte (240 x (320+96) x 18bits) internal RAM Incorporated LCD driver with 720 source outputs Compliant to COG Rev.0.5, July.31.2003, page 7 of 196 HD66781 Preliminary Block Diagram RGND GND AGND Index register (IR) Control register (CR) Address counter Vcc1 IOVcc IM3~1,I 0/ID M DACK* CS* RS WR/SCL RD* DB0/SDI DB1/SD0 DB2~17 GCS* GCL GDA Power-supply IC/ gate driver interface (serial) Vcom System Interface 18 bit 16 bit 9 bit 8 bit SPI 18 BGR Circuit 18 Write data latch Source line drive circuit 18 M alternation Latch circuit Latch circuit Latch circuit Graphic RAM (GRAM) 224,640 bytes 18 S1-720 Read data latch V63~0 VGS DDVDH VDH VTEST V0P V0N V63P V63N VMON PMON control circuit Grayscale circuit VSYNC HSYNC DOTCLK ENABLE PD0~17 External Display Interface VSYNC HSYNC DOTCLK ENABLE PD17-0 Timing generating circuit RESETO RESET* OSC3 OSC2 OSC1 TCS FLM SFTCLK1/CL1 SFTCLK2 DISPTMG M EQ DCLK BST CPG VDD Internal referene voltage generation circuit Vcc VDDTEST Regulator TEST1 VREFC1 VREFC2 VRTEST VREFD Rev.0.5, July.31.2003, page 8 of 196 VREF TEST2 TS8-0 HD66781 Preliminary Pin Functions Signals IM3~1, IM0/ID Number of I/O Pins 4 I Connected to GND or Vcc1 Functions Pins to select an interfacing mode with MPU. IM3 0 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 1 0 0 1 1 * IM0 0 1 0 1 * 0 1 0 1 0 1 * MPU-Interface Mode Setting disabled Setting disabled 80-system 16-bit interface DB Pins DB17-10, DB8-1 Colors 65,536 Note 1) 65,536 Note 2) 65,536 65,536 Note 2) 262,144 262,144 - Unused pins 80-system 8-bit interface DB17-10 (Big-endian) Serial peripheral interface (SPI) Setting disabled DB1-0 - - 80-system 8-bit interface DB17-10 (Little-endian) Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17-10 DB17-9 - Note 1) 262,144 colors available (max.) in 2-transfer mode. Note 2) 262,144 colors available (max.) in 3-transfer mode. CS* 1 I MPU Select the HD66781. Low: the HD66781 is selected and is accessible High: the HD66781 is not selected and is inaccessible Select the register. Low: Index/status registers High: Control registers Write strobe signal in the 80-system bus interface Write data at the "Low" level. In the Serial Peripheral Interface, a synchronizing clock signal. RD* DACK* 1 1 I I MPU MPU Read-strobe signal in the 80-system bus interface Read data at the "Low" level. Select the HD66781 in the DMA transfer single address mode. Low: Select the HD66781 (Accessible) High: Not Select the HD66781 (Inaccessible) DB0/SDI 1 I/O MPU 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Serial data input pin (SDI) in the Serial Peripheral Interface mode to input data on the rising edge of SCL signal. IOVcc IOVcc Vcc1 IOVcc RS 1 I MPU IOVcc WR*/SCL 1 I MPU - Rev.0.5, July.31.2003, page 9 of 196 HD66781 Signals DB1/SDO Number of I/O Pins 1 I/O Connected to MPU Functions Preliminary Unused pins IOVcc DB2~DB17 16 I/O MPU RESET* 1 I MPU or external R-C circuit 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Serial data output pin (SDO) in the Serial Peripheral Interface mode to output data on the falling edge of SCL signal. 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Reset pin. Initialize the LSI at the "Low" level. A power-on reset required after turning on the power. IOVcc Open RESETO1 RESETO2 OSC1 OSC2 ENABLE 2 O HD66783 or Output the same polarity level as RESET*. HD667P21 Control both HD66781 and HD66783 or HD66781 and HD667P21 by connecting to HD66783 or HD667P21. Oscillation resistor MPU or LCDC Connect an external resistor for R-C oscillation. 2 I or O I GND/ IOVcc 1 Data enable signal in the RGB interface mode. Low: Select (accessible) High: Not select (inaccessible) ENABLE signal inverts the polarity according to the setting of EPL resister. Set ENABLE inactive while it is not used and its level is fixed or the polarity is set with registers. Frame synchronizing signal. This signal is active low. The polarity of VSYNC is inverted by setting VSPL register. Set VSYNC inactive while it is not used and its level is fixed or the polarity is set with registers. VSYNC 1 I MPU or LCDC GND/ IOVcc HSYNC 1 I MPU or LCDC Line synchronizing signal. This signal is active low. The polarity of HSYNC is inverted by setting HSPL register. Set HSYNC inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc DOTCLK 1 I MPU or LCDC Dot clock signal. The timing of data input is determined at the rising edge. This signal is active low. The polarity of DOTCLK is inverted by setting DPL register. Set DOTCLK inactive while it is not used and its level is fixed or the polarity is set with registers. GND/ IOVcc PD0~PD17 18 I MPU or LCDC 18-bit bus for RGB data. 6-bit bus: PD17-PD12 16-bit bus: PD17-PD13 and PD11-PD1 18-bit bus: PD17-PD0 GND/ IOVcc Rev.0.5, July.31.2003, page 10 of 196 HD66781 Signals BST Number of I/O Pins 1 O Connected to MPU or LCDC Functions Preliminary Unused pins Output a pulse that indicates the start of blank (front porch). Open When writing data in synchronization with display scan, serve as a trigger signal. Amplitude: Vcc1 and GND. Output a voltage applied to liquid crystal. The correspondence between the RAM write address and source output signal is changeable with SS bit. When SS=0, data in the RAM address "h00000" are output from S1-3. When SS=1, data in the RAM address "h00000" are output from S718-720. S1, S4, S7, ... display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). Open S1~S720 720 O Liquid Crystal FLM1 FLM2 2 O O HD66783 or Output a frame head pulse. HD667P21 Open 2 CL11/ SFTCLK11 CL12/ SFTCLK12 SFTCLK21 2 SFTCLK22 HD66783 or Output a different signal according to the LTPS register setting. Open HD667P21 LTPS=0: Output a pulse of one line cycle. Connect to CL1 pin of HD66783. LTPS=1: Gate shift clock for LTPS. Output a pulse of 2-line cycles. HD667P21 Output a different signal according to the LTPS register setting. LTPS=0: Output is GND. No connection with HD66783 is required. LTPS=1: Gate shift clock for LTPS. Output a pulse of 2-line cycles. Open O DISPTMG1 2 DISPTMG2 O HD66783 or Gate off signal during partial display. HD667P21 Low: Voff output High: Normal output For an LTPS LCD panel, a control signal for the gate driver incorporated therein. Open M1 M2 EQ1 EQ2 2 2 O O HD66783 or Output alternating pulse. HD667P21 HD66783 or Make Vcom output Hi-z in Vcom transition timing during Vcom HD667P21 alternating drive. Low: Output VcomH or VcomL from Vcom High: Make Vcom output Hi-z HD66783 or Output step-up clocks. HD667P21 Open Open DCCLK1 DCCLK2 GCL1 GCL2 GDA1 GDA2 GCS1* GCS2* 2 2 O O Open HD66783 or Clock signal for making a serial transfer of values set in registers Open HD667P21 to gate driver/power supply IC. Output data from the falling edge of the clock. HD66783 or Data signal for making a serial transfer of values set in registers Open HD667P21 to gate driver/power supply IC. HD66783 or Select the HD66781. HD667P21 Low: Select the HD66781 (Serial transfer) High: Not select the HD66781 (Serial transfer not available) Open 2 2 O O Rev.0.5, July.31.2003, page 11 of 196 HD66781 Signals GND Number of I/O Pins 1 AGND 1 Connected to Power supply Power supply Functions Ground for the logic side. GND = 0V Preliminary Unused pins - When assembled on COG, connect to GND on the FPC to avoid effects from the noise. Ground for the I/O side and analogue circuits other than logic circuits and the internal GRAM, which operate with VDD voltage. AGND = 0V When assembled on COG, connect to GND on the FPC to avoid effects from the noise. - RGND 1 - Power supply Power supply Power supply Power supply Power supply Stabilizing Capacitor Ground for the internal RAM. RGND = 0V. When assembled on COG, connect to GND on the FPC to avoid effects from the noise. Supply with the power supply voltage for interface pins. IOVcc = 1.7~3.3V. IOVcc Vcc1 Vcc Power supply for internal logic regulator. Connect to an external power supply of Vcc = 2.5~3.3V. IOVcc Vcc1 Vcc Power supply voltage for a deep standby control circuit and the I/O side. IOVcc Vcc1 Vcc Reference voltage output for internal logic regulator. Leave open. Power supply output for an internal logic. Do not connect to other than stabilizing capacitors. - IOVcc Vcc 1 1 I - - - Vcc1 1 I VREF VDD DDVDH 1 1 1 O I/O I Open - HD66783 or Supply with a liquid crystal drive voltage through HD66783 or HD667P21 HD667P21. DDVDH = +4.0V~+5.9V HD66783 or A reference level for a grayscale voltage generation circuit. Can HD667P21 be supplied through HD66783 or HD667P21. GND or External Resistor A reference level for a grayscale voltage generation circuit. Connect to an external variable resistor to make a level adjustment for each panel. - VDH VGS 1 1 I I - Open Vcom 1 I HD66783 or Signal for equalization. Short-circuit all liquid crystal output HD667P21 (S1~S720) to Vcom level (Hi-z) while EQ = High. Leave open when Vcom < 0V. GND GND Open Open Open Open GND Test pins. Must be fixed to the GND level. Test pin. Must be fixed to the GND level. Test pin. Leave open. Test pins. Leave open. Test pin. Leave open. Test pin. Leave open. Test pins. Must be fixed to GND level. TEST1 TEST2 TSC OSC3 TS8-0 VTEST VRTEST VREFC1 VREFC2 2 1 1 9 1 1 2 I I O O O O I Open Open Open Open - Rev.0.5, July.31.2003, page 12 of 196 HD66781 Signals VDDTEST VREFD PMON VMON V0P V63P V0N V63N TIN1 TOUT1-3 TVcc1 TVcc2 Number of I/O Pins 1 1 1 1 2 2 1 3 2 I O O O Connected to GND Open Open Open Functions Test pin. Must be fixed to GND level. Test pin. Leave open. Test pin. Leave open. Test pin. Leave open. Test pins. Leave open. Test pins. Leave open. Test pin. Must be fixed to GND level. Test pins. Leave open. Test pins. Must be fixed to GND level. Preliminary Unused pins Open Open Open Open Open Open I or O Open I or O Open I O I GND Open GND Open DUMMY14 2 DUMMY15 DUMMY 1~13, 16~30 28 Dummy pads. DUMMY 14 and DUMMY 15 are short-circuited within the LSI. Available for measuring COG contact resistor. Dummy pads. Must be left open. IOVccDUM 3 1~3 Vcc1DUM1 2 Vcc1DUM2 AGNDDUM 4 1-4 TESTO1 TESTO2 2 O O O O Input pins Input pins Input pins Open Output an internal IOVcc level. When neighboring input pins are Open fixed to IOVcc, short-circuit them. Output an internal Vcc1 level. When neighboring input pins are fixed to Vcc1, short-circuit them. Output an internal AGND level. When neighboring input pins are fixed to AGND, short-circuit them. Test pins. Leave open. Open Open - Rev.0.5, July.31.2003, page 13 of 196 HD66781 HD66781 power-supply specification Item Input Voltage IOVcc Interface voltage 1 Voltage range +1.7V~+3.3V Specification Preliminary Power supply for signals interfacing with MPU or LCDC. Supply through the system. Power supply for CS*, RS, WR*/SCL, RD*, DB17-2, DB1/SDO, DB0/SDI, VSYNC, HSYNC, ENABLE, PD17-0. Connect on the FPC when using at the same electric potential with Vcc1. Vcc1 Interface voltage 2 +1.7V~+3.3V Power supply for signals interfacing with a gate driver/power supply IC and a deep standby mode control circuit that halts the logic regulator. Supply with the same electric potential with Vcc of HD66783 or HD667P21 though the system. Power supply for FLM1, FLM2, CL11/SFTCLK11, CL12/SFTCLK12, SFTCLK21, SFTCLK22, M1, M2, EQ1, EQ2, DCCLK1, DCCLK2, GCL1, GCL2, GDA1, GDA2, GCS1*, GCS2*, RESET*, RESETO1, RESETO2, DACK*, BST, M3-1, IM0/ID. Connect on the FPC when using at the same potential with IOVcc. Vcc Power supply for the logic regulator Power supply for the Internal logic - +2.5V~+3.3V Supply through the system. Connect on the FPC when using at the same electric potential with Vci of HD66783 or HD667P21. VDD 0V 0V 0V Generated from the internal logic regulator. Supply through the system is not required. GND for the internal logic circuit. Connect to GND on the FPC. GND for the internal GRAM. Connect to GND on the FPC. GND for the I/O side and analogue circuits other than logic circuits and the internal GRAM, which operate with VDD voltage. Connect to GND on the FPC. Connect to DDVDH of HD66783 or HD667P21. Connect to VREG1OUT of HD66783 or HD667P21. Connect to GND or variable resistor. - GND RGND AGND LCD drive voltage Source driver grayscale reference voltage LCD drive output DDVDH VDH VGS S1~ S720 V0~V63 grayscale level +4.5V~+5.9V +3.0V~ (DDVDH-0.5)V - Rev.0.5, July.31.2003, page 14 of 196 DUMMY30 DUMMY2 9 S1 S2 NO.1 S76 S77 DUMMY2 8 DUMMY2 7 (4-d) (3-a) HD667B81 PAD Arrangement NO.933 NO.931 NO.855 NO.853 (4-a) * Y * * * * * * * ** Y (2-a) NO.852 *oe Chip Size*F 16.94mm*~ 2.99mm *oe Chip Thickness*F 400mm(typ.) *oe PAD Coordinate : PAD center *oe Coordinate Origin : Chip Center *oe Bump Size : Au (1) 54mm*~ 106mm NO.1~NO.200 (2)26mm*~ 90mm NO.201~NO.281,NO.853~NO.933 (3)90mm*~ 26mm NO.282~NO.852 *oe Bump pitch : See PAD coordinate Au *oe Bump height : 15mm(typ.) Au *oe "No.X" in the Figure corresponds to the PAD No. in the PAD Coordinate Table. *oe Alignment Mark (1) Arranged Coordinate : 2 places Cell Name*F MARK_COGTGT (1-a) Coordinate (X,Y) = (-8199.6, 1324.3) (1-b) Coordinate (X,Y) = (8199.6, 1324.3) 100m* 50 30 30 40 30 (2) Arrangement Coordinate (2-a) Coordinate (X,Y) = (-8339.6, 1364.6) Cell Name*F MARK_EN_A 50m* (2-b) Coordinate (X,Y) = (8339.6, 1364.6) Cell Name*F MARK_EN_B 20 50mm (3) Arrangement Coordinate (3-a) Coordinate (X,Y) = (-8339.6, 1274.3) Cell Name*F MARK_L_A 5 10 25 25 10 5 10 5 70mm 80mm (3-b) Coordinate (X,Y) = (8339.6, 1274.3) Cell Name*F MARK_L_B 10 25 25 10 70mm *oe Long cell*F *Y (4) Arrangement Coordinate : 4 places Cell Name*F ZBASFLONGSCALELCD (4-a) Coordinate (X,Y) = (-8339.6, -1197.9) (4-b) Coordinate (X,Y) = (8339.6, -1197.9) (4-c) Coordinate (X,Y) = (8339.6, 1197.9) (4-c) Coordinate (X,Y) = (-8339.6, 1197.9) *oe Short cell*F * (5) Arrangement Coordinate : 1 place (5-a) Coordinate (X,Y) = (8339.6, -1276.1) Cell Name*F ZBSHORTSCALE_L0106 BUMP Top View Chip DUMMY1 TESTO1 FLM1 SFTCLK21 CL11/SFTCLK11 M1 EQ1 DISPTMG1 GDA1 GCS1* GCL1 DCCLK1 RESETO1 DUMMY2 RESET* BST DUMMY3 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 IOVccDUM1 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI IOVccDUM2 RD* WR*/SCL RS CS* DUMMY4 DACK* Vcc1DUM1 VSYNC HSYNC DOTCLK ENABLE PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 IOVcc IOVcc IOVcc IOVcc Vcc1 Vcc1 Vcc1 Vcc1 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND AGND AGND AGND AGND AGND AGND AGND AGND DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH V0P V0N V63P V63N VGS VDH PMON VMON VTEST Vcom Vcom DUMMY5 VREFD VRTEST VREF DUMMY6 VREFC1 VREFC2 VDDTEST DUMMY7 TSC AGNDDUM1 DUMMY8 OSC1 DUMMY9 DUMMY10 OSC2 DUMMY11 Vcc1DUM2 OSC3 IOVccDUM3 IM0/ID IM1 IM2 IM3 AGNDDUM2 TEST1 TEST2 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 RESETO2 DCCLK2 GCL2 GCS2* GDA2 DISPTMG2 EQ2 M2 CL12/SFTCLK12 SFTCLK22 FLM2 AGNDDUM3 TIN1 TOUT1 TOUT2 TOUT3 AGNDDUM4 TVcc1 TVcc2 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 NO.199 TESTO2 DUMMY17 NO.200 NO.2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *i 1-a*j * * * DUMMY26 * S78 DUMMY25 S79 NO.850 100m* 50 30 25 25 80mm 70mm 40 HD667B81 Laced Output Arrangement Top View 70mm 10 25 25 10 5 10 TypeCode : HD667B81 Short-circuit * * * S642 * DUMMY24 * DUMMY22 S643 NO.285 *i 1-b*j * * * ** Y DUMMY23 * * * Y * * * (2-b) NO.282 DUMMY1 8 DUMMY1 9 S720 S719 NO.201 NO.203 S645 S644 DUMMY2 0 DUMMY2 1 (4-c) (3-b) NO.279 (5-a) (4-b) NO.281 HD66781 Preliminary Pad Coordinate Unit : m pad No pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DUMMY1 TESTO1 FLM1 SFTCLK21 CL11/SFTCLK11 M1 EQ1 DISPTMG1 GDA1 GCS1* GCL1 DCCLK1 RESETO1 DUMMY2 RESET* BST DUMMY3 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 IOVccDUM1 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI IOVccDUM2 RD* WR*/SCL RS CS* DUMMY4 DACK* Vcc1DUM1 VSYNC HSYNC DOTCLK ENABLE PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 IOVcc IOVcc IOVcc IOVcc Vcc1 Vcc1 Vcc1 Vcc1 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND AGND AGND AGND AGND AGND AGND AGND AGND -7960.0 -7880.0 -7800.0 -7720.0 -7640.0 -7560.0 -7480.0 -7400.0 -7320.0 -7240.0 -7160.0 -7080.0 -7000.0 -6920.0 -6840.0 -6760.0 -6680.0 -6600.0 -6520.0 -6440.0 -6360.0 -6280.0 -6200.0 -6120.0 -6040.0 -5960.0 -5880.0 -5800.0 -5720.0 -5640.0 -5560.0 -5480.0 -5400.0 -5320.0 -5240.0 -5160.0 -5080.0 -5000.0 -4920.0 -4840.0 -4760.0 -4680.0 -4600.0 -4520.0 -4440.0 -4360.0 -4280.0 -4200.0 -4120.0 -4040.0 -3960.0 -3880.0 -3800.0 -3720.0 -3640.0 -3560.0 -3480.0 -3400.0 -3320.0 -3240.0 -3160.0 -3080.0 -3000.0 -2920.0 -2840.0 -2760.0 -2680.0 -2600.0 -2520.0 -2440.0 -2360.0 -2280.0 -2200.0 -2120.0 -2040.0 -1960.0 -1880.0 -1800.0 -1720.0 -1640.0 -1560.0 -1480.0 -1400.0 -1320.0 -1240.0 -1160.0 -1080.0 -1000.0 -920.0 -840.0 -760.0 -680.0 -600.0 -520.0 -440.0 -360.0 -280.0 -200.0 -120.0 -40.0 40.0 120.0 200.0 280.0 360.0 440.0 520.0 600.0 680.0 760.0 840.0 920.0 1000.0 1080.0 1160.0 1240.0 1320.0 1400.0 1480.0 1560.0 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH V0P V0N V63P V63N VGS VDH PMON VMON VTEST Vcom Vcom DUMMY5 VREFD VRTEST VREF DUMMY6 VREFC1 VREFC2 VDDTEST DUMMY7 TSC AGNDDUM1 DUMMY8 OSC1 DUMMY9 DUMMY10 OSC2 DUMMY11 Vcc1DUM2 OSC3 IOVccDUM3 IM0/ID IM1 IM2 IM3 AGNDDUM2 TEST1 TEST2 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 RESETO2 DCCLK2 GCL2 GCS2* GDA2 DISPTMG2 EQ2 M2 CL12/SFTCLK12 SFTCLK22 FLM2 AGNDDUM3 TIN1 TOUT1 TOUT2 TOUT3 AGNDDUM4 TVcc1 TVcc2 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 TESTO2 DUMMY17 DUMMY18 DUMMY19 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687 S686 S685 S684 S683 1640.0 1720.0 1800.0 1880.0 1960.0 2040.0 2120.0 2200.0 2280.0 2360.0 2440.0 2520.0 2600.0 2680.0 2760.0 2840.0 2920.0 3000.0 3080.0 3160.0 3240.0 3320.0 3400.0 3480.0 3560.0 3640.0 3720.0 3800.0 3880.0 3960.0 4040.0 4120.0 4200.0 4280.0 4360.0 4440.0 4520.0 4600.0 4680.0 4760.0 4840.0 4920.0 5000.0 5080.0 5160.0 5240.0 5320.0 5400.0 5480.0 5560.0 5640.0 5720.0 5800.0 5880.0 5960.0 6040.0 6120.0 6200.0 6280.0 6360.0 6440.0 6520.0 6600.0 6680.0 6760.0 6840.0 6920.0 7000.0 7080.0 7160.0 7240.0 7320.0 7400.0 7480.0 7560.0 7640.0 7720.0 7800.0 7880.0 7960.0 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1356.3 -1132.4 -1104.4 -1076.4 -1048.4 -1020.4 -992.4 -964.4 -936.4 -908.4 -880.4 -852.4 -824.4 -796.4 -768.4 -740.4 -712.4 -684.4 -656.4 -628.4 -600.4 -572.4 -544.4 -516.4 -488.4 -460.4 -432.4 -404.4 -376.4 -348.4 -320.4 -292.4 -264.4 -236.4 -208.4 -180.4 -152.4 -124.4 -96.4 -68.4 -40.4 241 S682 242 S681 243 S680 244 S679 245 S678 246 S677 247 S676 248 S675 249 S674 250 S673 251 S672 252 S671 253 S670 254 S669 255 S668 256 S667 257 S666 258 S665 259 S664 260 S663 261 S662 262 S661 263 S660 264 S659 265 S658 266 S657 267 S656 268 S655 269 S654 270 S653 271 S652 272 S651 273 S650 274 S649 275 S648 276 S647 277 S646 278 S645 279 S644 280 DUMMY20 281 DUMMY21 282 DUMMY22 283 DUMMY23 284 DUMMY24 285 S643 286 S642 287 S641 288 S640 289 S639 290 S638 291 S637 292 S636 293 S635 294 S634 295 S633 296 S632 297 S631 298 S630 299 S629 300 S628 301 S627 302 S626 303 S625 304 S624 305 S623 306 S622 307 S621 308 S620 309 S619 310 S618 311 S617 312 S616 313 S615 314 S614 315 S613 316 S612 317 S611 318 S610 319 S609 320 S608 321 S607 322 S606 323 S605 324 S604 325 S603 326 S602 327 S601 328 S600 329 S599 330 S598 331 S597 332 S596 333 S595 334 S594 335 S593 336 S592 337 S591 338 S590 339 S589 340 S588 341 S587 342 S586 343 S585 344 S584 345 S583 346 S582 347 S581 348 S580 349 S579 350 S578 351 S577 352 S576 353 S575 354 S574 355 S573 356 S572 357 S571 358 S570 359 S569 360 S568 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 8204.6 8339.6 7980.0 7952.0 7924.0 7896.0 7868.0 7840.0 7812.0 7784.0 7756.0 7728.0 7700.0 7672.0 7644.0 7616.0 7588.0 7560.0 7532.0 7504.0 7476.0 7448.0 7420.0 7392.0 7364.0 7336.0 7308.0 7280.0 7252.0 7224.0 7196.0 7168.0 7140.0 7112.0 7084.0 7056.0 7028.0 7000.0 6972.0 6944.0 6916.0 6888.0 6860.0 6832.0 6804.0 6776.0 6748.0 6720.0 6692.0 6664.0 6636.0 6608.0 6580.0 6552.0 6524.0 6496.0 6468.0 6440.0 6412.0 6384.0 6356.0 6328.0 6300.0 6272.0 6244.0 6216.0 6188.0 6160.0 6132.0 6104.0 6076.0 6048.0 6020.0 5992.0 5964.0 5936.0 5908.0 5880.0 5852.0 5824.0 5796.0 -12.4 15.6 43.6 71.6 99.6 127.6 155.6 183.6 211.6 239.6 267.6 295.6 323.6 351.6 379.6 407.6 435.6 463.6 491.6 519.6 547.6 575.6 603.6 631.6 659.6 687.6 715.6 743.6 771.6 799.6 827.6 855.6 883.6 911.6 939.6 967.6 995.6 1023.6 1051.6 1079.6 1107.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 5768.0 5740.0 5712.0 5684.0 5656.0 5628.0 5600.0 5572.0 5544.0 5516.0 5488.0 5460.0 5432.0 5404.0 5376.0 5348.0 5320.0 5292.0 5264.0 5236.0 5208.0 5180.0 5152.0 5124.0 5096.0 5068.0 5040.0 5012.0 4984.0 4956.0 4928.0 4900.0 4872.0 4844.0 4816.0 4788.0 4760.0 4732.0 4704.0 4676.0 4648.0 4620.0 4592.0 4564.0 4536.0 4508.0 4480.0 4452.0 4424.0 4396.0 4368.0 4340.0 4312.0 4284.0 4256.0 4228.0 4200.0 4172.0 4144.0 4116.0 4088.0 4060.0 4032.0 4004.0 3976.0 3948.0 3920.0 3892.0 3864.0 3836.0 3808.0 3780.0 3752.0 3724.0 3696.0 3668.0 3640.0 3612.0 3584.0 3556.0 3528.0 3500.0 3472.0 3444.0 3416.0 3388.0 3360.0 3332.0 3304.0 3276.0 3248.0 3220.0 3192.0 3164.0 3136.0 3108.0 3080.0 3052.0 3024.0 2996.0 2968.0 2940.0 2912.0 2884.0 2856.0 2828.0 2800.0 2772.0 2744.0 2716.0 2688.0 2660.0 2632.0 2604.0 2576.0 2548.0 2520.0 2492.0 2464.0 2436.0 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 Rev.0.5, July.31.2003, page 16 of 196 HD66781 pad No Preliminary pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name X Y 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 2408.0 2380.0 2352.0 2324.0 2296.0 2268.0 2240.0 2212.0 2184.0 2156.0 2128.0 2100.0 2072.0 2044.0 2016.0 1988.0 1960.0 1932.0 1904.0 1876.0 1848.0 1820.0 1792.0 1764.0 1736.0 1708.0 1680.0 1652.0 1624.0 1596.0 1568.0 1540.0 1512.0 1484.0 1456.0 1428.0 1400.0 1372.0 1344.0 1316.0 1288.0 1260.0 1232.0 1204.0 1176.0 1148.0 1120.0 1092.0 1064.0 1036.0 1008.0 980.0 952.0 924.0 896.0 868.0 840.0 812.0 784.0 756.0 728.0 700.0 672.0 644.0 616.0 588.0 560.0 532.0 504.0 476.0 448.0 420.0 392.0 364.0 336.0 308.0 280.0 252.0 224.0 196.0 168.0 140.0 112.0 84.0 56.0 28.0 0.0 -28.0 -56.0 -84.0 -112.0 -140.0 -168.0 -196.0 -224.0 -252.0 -280.0 -308.0 -336.0 -364.0 -392.0 -420.0 -448.0 -476.0 -504.0 -532.0 -560.0 -588.0 -616.0 -644.0 -672.0 -700.0 -728.0 -756.0 -784.0 -812.0 -840.0 -868.0 -896.0 -924.0 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 -952.0 -980.0 -1008.0 -1036.0 -1064.0 -1092.0 -1120.0 -1148.0 -1176.0 -1204.0 -1232.0 -1260.0 -1288.0 -1316.0 -1344.0 -1372.0 -1400.0 -1428.0 -1456.0 -1484.0 -1512.0 -1540.0 -1568.0 -1596.0 -1624.0 -1652.0 -1680.0 -1708.0 -1736.0 -1764.0 -1792.0 -1820.0 -1848.0 -1876.0 -1904.0 -1932.0 -1960.0 -1988.0 -2016.0 -2044.0 -2072.0 -2100.0 -2128.0 -2156.0 -2184.0 -2212.0 -2240.0 -2268.0 -2296.0 -2324.0 -2352.0 -2380.0 -2408.0 -2436.0 -2464.0 -2492.0 -2520.0 -2548.0 -2576.0 -2604.0 -2632.0 -2660.0 -2688.0 -2716.0 -2744.0 -2772.0 -2800.0 -2828.0 -2856.0 -2884.0 -2912.0 -2940.0 -2968.0 -2996.0 -3024.0 -3052.0 -3080.0 -3108.0 -3136.0 -3164.0 -3192.0 -3220.0 -3248.0 -3276.0 -3304.0 -3332.0 -3360.0 -3388.0 -3416.0 -3444.0 -3472.0 -3500.0 -3528.0 -3556.0 -3584.0 -3612.0 -3640.0 -3668.0 -3696.0 -3724.0 -3752.0 -3780.0 -3808.0 -3836.0 -3864.0 -3892.0 -3920.0 -3948.0 -3976.0 -4004.0 -4032.0 -4060.0 -4088.0 -4116.0 -4144.0 -4172.0 -4200.0 -4228.0 -4256.0 -4284.0 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 -4312.0 -4340.0 -4368.0 -4396.0 -4424.0 -4452.0 -4480.0 -4508.0 -4536.0 -4564.0 -4592.0 -4620.0 -4648.0 -4676.0 -4704.0 -4732.0 -4760.0 -4788.0 -4816.0 -4844.0 -4872.0 -4900.0 -4928.0 -4956.0 -4984.0 -5012.0 -5040.0 -5068.0 -5096.0 -5124.0 -5152.0 -5180.0 -5208.0 -5236.0 -5264.0 -5292.0 -5320.0 -5348.0 -5376.0 -5404.0 -5432.0 -5460.0 -5488.0 -5516.0 -5544.0 -5572.0 -5600.0 -5628.0 -5656.0 -5684.0 -5712.0 -5740.0 -5768.0 -5796.0 -5824.0 -5852.0 -5880.0 -5908.0 -5936.0 -5964.0 -5992.0 -6020.0 -6048.0 -6076.0 -6104.0 -6132.0 -6160.0 -6188.0 -6216.0 -6244.0 -6272.0 -6300.0 -6328.0 -6356.0 -6384.0 -6412.0 -6440.0 -6468.0 -6496.0 -6524.0 -6552.0 -6580.0 -6608.0 -6636.0 -6664.0 -6692.0 -6720.0 -6748.0 -6776.0 -6804.0 -6832.0 -6860.0 -6888.0 -6916.0 -6944.0 -6972.0 -7000.0 -7028.0 -7056.0 -7084.0 -7112.0 -7140.0 -7168.0 -7196.0 -7224.0 -7252.0 -7280.0 -7308.0 -7336.0 -7364.0 -7392.0 -7420.0 -7448.0 -7476.0 -7504.0 -7532.0 -7560.0 -7588.0 -7616.0 -7644.0 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 DUMMY25 DUMMY26 DUMMY27 DUMMY28 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY29 DUMMY30 -7672.0 -7700.0 -7728.0 -7756.0 -7784.0 -7812.0 -7840.0 -7868.0 -7896.0 -7924.0 -7952.0 -7980.0 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 -8204.6 -8339.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1229.6 1364.6 1107.6 1079.6 1051.6 1023.6 995.6 967.6 939.6 911.6 883.6 855.6 827.6 799.6 771.6 743.6 715.6 687.6 659.6 631.6 603.6 575.6 547.6 519.6 491.6 463.6 435.6 407.6 379.6 351.6 323.6 295.6 267.6 239.6 211.6 183.6 155.6 127.6 99.6 71.6 43.6 15.6 -12.4 -40.4 -68.4 -96.4 -124.4 -152.4 -180.4 -208.4 -236.4 -264.4 -292.4 -320.4 -348.4 -376.4 -404.4 -432.4 -460.4 -488.4 -516.4 -544.4 -572.4 -600.4 -628.4 -656.4 -684.4 -712.4 -740.4 -768.4 -796.4 -824.4 -852.4 -880.4 -908.4 -936.4 -964.4 -992.4 -1020.4 -1048.4 -1076.4 -1104.4 -1132.4 Alignment Mark L-type (Positive) L-type (Negative) Circle (Positive) Circle (Negative) Cross X Y -8339.6 8339.6 -8339.6 8339.6 -8199.6 8199.6 1274.3 1274.3 1364.6 1364.6 1324.3 1324.3 Unit : m Rev.0.5, July.31.2003, page 17 of 196 HD66781 Preliminary Bump Arrangement 26 30 26 90 S1~S720 135 45 S=2340um2 90 28 28 Unit : um 54 I/O pins (No1 ~ 200) 106 S=5724um2 Min.80 Unit : um Rev.0.5, July.31.2003, page 18 of 196 DUMMY18 DUMMY19 S720 S719 1 1 1 1 1 S645 S644 DUMMY20 DUMMY21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 80-system 18-bit interface 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 *... 10ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GND *... 10ohm *... 5ohm *... 20ohm 1uF/3V/B *... 5ohm 1 1 1 1 1 1 1 1 1 1 1 1 *... 10ohm 1 1 1 1 1 1 1 1 1 1 1.7~3.3V Vcc1(781)=Vcc(783) 1.7~3.3V *... *... 20ohm IOVcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 ENABLE DOTCLK HSYNC VSYNC DACK* CS* RS WR*/SCL RD* DB0/SDI DB1/SDO DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 BST RESET* 20ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DUMMY17 TESTO2 DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 TVcc2 TVcc1 AGNDDUM4 TOUT3 TOUT2 TOUT1 TIN1 AGNDDUM3 FLM2 SFTCLK22 CL12/SFTCLK12 M2 EQ2 DISPTMG2 GDA2 GCS2* GCL2 DCCLK2 RESETO2 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TEST2 TEST1 AGNDDUM2 IM3 IM2 IM1 IM0/ID IOVccDUM3 OSC3 Vcc1DUM2 DUMMY11 OSC2 DUMMY10 DUMMY9 OSC1 DUMMY8 AGNDDUM1 TSC DUMMY7 VDDTEST VREFC2 VREFC1 DUMMY6 VREF VRTEST VREFD DUMMY5 Vcom Vcom VTEST VMON PMON VDH VGS V63N V63P V0N V0P DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH AGND AGND AGND AGND AGND AGND AGND AGND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc1 Vcc1 Vcc1 Vcc1 IOVcc IOVcc IOVcc IOVcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 ENABLE DOTCLK HSYNC VSYNC Vcc1DUM1 DACK* DUMMY4 CS* RS WR*/SCL RD* IOVccDUM2 DB0/SDI DB1/SDO DB2 DB3 DB4 DB5 DB6 DB7 DB8 IOVccDUM1 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DUMMY3 BST RESET* DUMMY2 RESETO1 DCCLK1 GCL1 GCS1* GDA1 DISPTMG1 EQ1 M1 CL11/SFTCLK11 SFTCLK21 FLM1 TESTO1 DUMMY1 1 1 1 Short-circuit DUMMY14 and DUMMY15 Within LSI 1 DUMMY22 DUMMY23 S643 S642 Example of connecting HD66781 and HD66783 Note: This is an example of connecting HD66781 and HD66783 when these drivers are used as a set. The bottom views show an example of pin arrangements. See the pad cooridnation of each product for more accurate and detailed reference to the number of pads and the coordination. The validity of this connection example is not confirmed. It is necessary to throughly check the operation and the display quality before use. To opposing electrodes on the panel(Vcom) HD66781 (Bottom View) Laced Output Arrangement Connect on the FPC. Connect on the FPC. Connect on the FPC. , VR* 30V 30V a-Si TFT Source Electrode IOVcc = 1.7V~3.3V (HD66781) Vcc1 = 1.7~3.3V (HD66781) Vcc = 2.5~3.3V (HD66781) VCC = 1.7~3.3V (HD667P21) VCI = 2.5~3.3V (HD667P21) Supply a same potential to Vcc1 of HD66781 and VCC of HD66783. Make sure that IOVcc*... Vcc1*... Vcc (HD66781). 1 1 1 1 S79 S78 DUMMY25 DUMMY26 1 1 1 1 1 1 1 1 S2 S1 DUMMY29 DUMMY30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DUMMY27 DUMMY28 S77 S76 1 1 1 1 1 > 200k 1 1 1uF/6V/B *... 15ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 *... 1uF/10V/B *... *... *... *... *... *... *... 1uF/10V/B 30ohm 30ohm 30ohm 30ohm 30ohm 30ohm 20ohm 20ohm 1uF/6V/B 1uF/6V/B 1 1 1 1 1 1 1 1 1uF/10V/B *... 10ohm VF<0.4V/20mA at 25*Z 1 1uF/25V/B 1uF/6V/B 1uF/6V/B *... *... *... 30ohm 30ohm 15ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1uF/6V/B 1uF/6V/B *... *... 15ohm 30ohm 1uF/25V/B VF<0.4V/20mA at 25*Z , VR* *... 10ohm *... *... Vcc(781)=Vci(783) 2.5~3.3V *... 15ohm 30ohm 20ohm *... 50ohm DMY36 DMY35 VREG1OUT GND GND GND GND DMY34 DMY33 C22+ C22+ C22C22C21+ C21+ C21C21C12+ C12+ C12C12C11+ C11+ C11+ C11C11C11DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DMY32 VGH VGH DMY31 VCOMH2 VCOMH2 VCIOUT VCIOUT VCIOUT VCIOUT VCOML2 VCOML2 VCOML2 VCOML2 VCL VCL VGL VGL VGL VGL VGL VGL AGND AGND AGND AGND VCC VCC VCI VCI VCI VCILVL TMP TMP TMN TMN VCOM2 VCOM2 VCOM2 VCOM2 DMY30 DMY29 DMY28 DMY27 DMY26 DMY25 TESTA12 TESTA2 TESTA42 DMY24 DMY23 DMY22 TG328 G328 G327 G326 1 1 1 1 1 1 1 1 DMY12 DMY13 G1 G2 G3 G4 G5 G6 HD667B83 (Bottom View) Laced Output Arrangement Connect on the FPC. Gate electrode Short-circuit DMY22 and DMY23 within LSI Short-circuit TG328 and G328 within LSI 1 1 1 1 1 1 1 1 1 1 Bottom View (Non Bump View) Chip G284 G283 DMY21 DMY20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G229 DMY14 DMY15 Glass G272 G273 G274 G275 G276 G277 G278 G279 G280 G281 G282 DMY18 DMY19 DMY16 DMY17 G230 G231 G232 G233 G234 G235 Gate electrode DUMMY18 DUMMY19 S720 S719 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 80-system 18-bit interface *... 10ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GND *... 10ohm *... 5ohm *... 20ohm 1uF/3V/B *... 5ohm 1 1 1 1 1 1 1 1 1 1 1 1 *... 10ohm 1 1 1 1 1 1 1 1 1 1 1.7~3.3V Vcc1(781)=VCC(7P21) 1.7~3.3V *... 20ohm IOVcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 ENABLE DOTCLK HSYNC VSYNC DACK* CS* RS WR*/SCL RD* DB0/SDI DB1/SDO DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 BST RESET* *... 20ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DUMMY17 TESTO2 DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 TVcc2 TVcc1 AGNDDUM4 TOUT3 TOUT2 TOUT1 TIN1 AGNDDUM3 FLM2 SFTCLK22 CL12/SFTCLK12 M2 EQ2 DISPTMG2 GDA2 GCS2* GCL2 DCCLK2 RESETO2 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TEST2 TEST1 AGNDDUM2 IM3 IM2 IM1 IM0/ID IOVccDUM3 OSC3 Vcc1DUM2 DUMMY11 OSC2 DUMMY10 DUMMY9 OSC1 DUMMY8 AGNDDUM1 TSC DUMMY7 VDDTEST VREFC2 VREFC1 DUMMY6 VREF VRTEST VREFD DUMMY5 Vcom Vcom VTEST VMON PMON VDH VGS V63N V63P V0N V0P DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH AGND AGND AGND AGND AGND AGND AGND AGND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc1 Vcc1 Vcc1 Vcc1 IOVcc IOVcc IOVcc IOVcc PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 ENABLE DOTCLK HSYNC VSYNC Vcc1DUM1 DACK* DUMMY4 CS* RS WR*/SCL RD* IOVccDUM2 DB0/SDI DB1/SDO DB2 DB3 DB4 DB5 DB6 DB7 DB8 IOVccDUM1 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DUMMY3 BST RESET* DUMMY2 RESETO1 DCCLK1 GCL1 GCS1* GDA1 DISPTMG1 EQ1 M1 CL11/SFTCLK11 SFTCLK21 FLM1 TESTO1 DUMMY1 S645 S644 DUMMY20 DUMMY21 1 1 1 1 Short-circuit DUMMY14 and DUMMY15 within LSI 1 1 1 DUMMY22 DUMMY23 S643 S642 Example of connecting HD66781 and HD667P21 To opposing electrodes on the panel(Vcom HD66781 (Bottom View) DUMMY30 DUMMY29 S1 S2 S76 S77 DUMMY28 DUMMY27 Connect on the FCP. Connect on the FCP. SIN7 , VR* 30V VF<0.4V/20mA at 25*Z Poly-Si TFT Laced Output Source Electrode IOVcc = 1.7V~3.3V (HD66781) Vcc1 = 1.7~3.3V (HD66781) Vcc = 2.5~3.3V (HD66781) VCC = 1.7~3.3V (HD667P21) VCI = 2.5~3.3V (HD667P21) Supply a same potential to Vcc1 of HD66781 and VCC of HD667P21. Make sure that IOVcc*... Vcc1*... Vcc (HD66781). 1 1 1 1 S79 S78 DUMMY25 DUMMY26 1 1 1 1 1 1 1 1 Fix to GND DMY4 1 111111111111111111111 1 DMY7 1 1 1 1 1 1 Vcc(781)=Vci(7P21) *... 2.5* 3.3V *... 5ohm 10ohm 1 1 1 1 1 1 1 1 1 1uF/6V/B *... 5ohm > 200kW *... 10ohm *... *... *... *... *... *... *... 40ohm 10ohm 40ohm 50ohm 20ohm 20ohm 40ohm *... 20ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1uF/6V/B 1uF/10V/B VF<0.4V/20mA at 25*Z , VR* 30V 1uF/25V/B 1uF/25V/B 1uF/6V/B 1uF/6V/B 1uF/6V/B VF<0.4V/20mA at 25*Z , VR* 30V 1uF/25V/B 1uF/25V/B *... 1uF/6V/B *... *... 1uF/6V/B *... *... 1uF/10V/B *... *... 1uF/10V/B *... 30~50ohm 1 1 1 10ohm 1 1 1 1 1 1 1 1 10ohm 20ohm 20ohm 40ohm 40ohm 40ohm 40ohm 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DMY3 Vci Vci Vci Vci Vci VCC VCC GND GND GND GND GND GND VciOUT Vci1 Vci1 VCOMR VREG1 VREG1OUT VLOUT1 DDVDH DDVDH DDVDH VLOUT2 VLOUT2 VGH VGH VCOMH VCOMH VCOML VCOML VCL VCL VLOUT4 VLOUT3 VLOUT3 VLOUT3 VGL VGL C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ DMY2 DMY6 CLC CLB CLA SIN1 SIN2 SIN3 GNDDMY2 VCCDMY1 M SIN5 GNDDNY1 EQ SIN4 GDA GCS* GCL DCCLK RESET* SIN7 DMY5 DMY8 DMY9 DMY10 DMY11 DMY12 GNDDMY3 GNDDMY4 GNDDMY5 TESTM TESTL TESTG VCCDMY2 VCCDMY3 VTEST SOUT8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HD667P21 (Bottom View) Connect on the FPC. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 To opposing electrodes on the panel(Vcom) Vcom Vcom CLCO CLBO CLAO SOUT7 SOUT6 SOUT5 SOUT4 SOUT3 SOUT2 SOUT1 SOUT1 DMY30 DMY31 DMY32 DMY33 DMY34 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Gate Circuit DMYP 1 1111111111111111111111 1 DMY35 DMY36 DMY37 DMY38 DMY39 DMY40 DMY41 DMY42 DMY43 DMY44 DMY45 TESTA1 TESTA2 TESTA3 TESTA4 TESTA5 TESTA6 TESTR TDCB TDCA Vcom Vcom DMY46 Bottom View (Non Bump View) Chip Glass HD66781 Preliminary Block Function (1) System interface The HD66781 has 2 kinds of high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus interfaces and Serial Peripheral Interface (SPI) ports. The 8-bit bus interface is compliant to both big and little endian data outputs from the microcomputer. The interface mode is selected with the IM3-0 pins. The HD66781 incorporates 16-bit index register (IR), write-data register (WDR), and 16-bit read-data register (RDR). The IR stores index information from the control register and GRAM. The WDR temporarily stores data to write into the control register and GRAM, and the RDR temporarily stores data read from GRAM. Data written into GRAM from MPU is first written into the WDR and then automatically written to GRAM by internal operation. Since data are read through the RDR from GRAM, the data that are read out first are invalid and the ensuing data are read out normally. The execution time for the instructions other than oscillation start is 0-clock cycle, which enables writing instructions consecutively. Table 1 Register Selection (8/9/16/18 parallel interface) Operation Write index to IR. Read internal status Write to control registers/GRAM through WDR Read from GRAM through RDR 80-system bus WR* 0 1 0 1 RD* 1 0 1 0 RS 0 0 1 1 Table 2 Register Selection (SPI) Operation Write index to IR. Read internal status Write to control registers/GRAM through WDR Read from GRAM through RDR Start byte RW 0 1 0 1 RS 0 0 0 1 Rev.0.5, July.31.2003, page 21 of 196 HD66781 Preliminary The HD66781 incorporates DMA single address mode interface to keep control on the bus occupation ratio when transferring a large volume of data. The DMA controller supporting a single address mode controls the DACK pin of HD66781 to recognize out-enable signal (OE) for SRAM as a write strobe signal. The HD66781 enables data transfer with less bus cycle by using a same bus cycle for a readout operation from an external SRAM and a write operation to HD66781. See "DMA transfer single address mode" (p.131) for details on controlling the execution of transfer and conditions in using this mode. (2) External Display Interface (RGB I/F, VSYNC I/F) The HD66781 incorporates RGB and VSYNC interfaces as an external interface for displaying moving pictures. When the RGB-I/F is selected, the operation is synchronized with externally supplied signals, VSYN C, HSYNC, and DOTCLK. The display data (PD17-0) are written in accordance with the data enable signal (ENABLE). Accordingly, the display on the screen does not flicker when RAM data are being updated internally. When the VSYNC-I/F is selected, the operation is synchronized with internal clocks except frame synchronization, which is synchronized with VSYNC signal. The display data is written to GRAM through a system interface. In this case, there are constraints on the speed and methods of updating RAM data when the VSYNC I/F is selected. For details, see the "External Display Interface" section (p.139). The switch from and to the system interface is made through instructions. An optimum interface can be selected for the kind of display (still and/or moving pictures). The display data are all written to GRAM through the RGB-I/F. This enables transmission of data only when the display on the screen is being updated, and thereby reduces the data transmission as well as consumption of power when a moving picture is displayed. (3) Address Counter (AC) The address counter (AC) assigns the address to GRAM. When a set-address instruction is written to the IR, the address information is sent from the IR to the AC. After writing data into GRAM, the AC is automatically incremented or decremented by 1, while after data are read form GRAM, the AC is not updated. Window address function enables data write only in the rectangular area of GRAM specified by the window address. (4) Graphic RAM (GRAM) GRAM is a graphics RAM that stores 224,640-byte bit-pattern data, where one pixel is expressed by 18 bits. Maximum 240 RGB x 320 can be displayed by using both main/sub panels. Besides data of 240 RGB x 320 lines for a base image, it can store OSD data of 240 RGB x 96 lines. The allocation of the numbers of lines for a base image and an OSD image is changeable. (5) Grayscale Voltage Generation Circuit The grayscale voltage generation circuit generates an LCD drive voltage according to the grayscale level set in the -correction register. Simultaneously 262,144 colors are available for display. Rev.0.5, July.31.2003, page 22 of 196 HD66781 (6) Timing generator Preliminary Timing generator generates a timing signal for the operation of internal circuits such as GRAM. The timing for display operation such as RAM read and the internal operation timing such as access from MPU are generated in a way to avoid mutual interfere. Also the signals interfacing with gate driver/power supply IC (M, FLM, CL1/SFTCLK1, SFTCLK2, EQ, DCCLK, and DISPTMG) are generated. (7) Oscillation Circuit (OSC) The HD66781 generates R-C oscillation simply by placing an external oscillation-resistor between the OSC1 and OSC2 pins. The oscillation frequency is changeable with the value of external resistor. Adjust oscillation frequency in accordance to an operation voltage, display size, and frame frequency. During the standby mode, the R-C oscillation is halted to reduce power consumption. For details, see "Oscillation Circuit" (p.173). (8) Liquid Crystal Display Driver Circuit The LCD driver circuit consists of a 720-output source driver (S1 ~ S720). Display pattern data are latched when 720-bit data arrive. The latched data controls the source driver and generates drive waveforms. The shift direction of 720-bit output from source driver is changeable with SS bit. Select an appropriate shift direction for the assembly. (9) Gate driver/power supply IC interfacing circuit Gate driver/power supply IC interfacing circuit is a serial interface circuit to interface with the HD66783 and the HD667P21. When making settings for instructions to the HD66783 or the HD667P21 though the HD66781, values set in the register of HD66781 are transferred through this serial interface circuit. The transfer starts by making a serial transfer ENABLE setting. Both transfer of instruction to the HD66783/HD667P21 and read out from the HD66781 are impossible during standby mode. For details, see "Gate Driver/Power Supply IC interface control" (p.70). (10) Internal Logic Power Supply Regulator Internal logic power supply regulator generates power supply VDD for the internal logic. Rev.0.5, July.31.2003, page 23 of 196 HD66781 Preliminary GRAM Address MAP Relation between GRAM addresses and Screen positions (SS=0, BGR=0) Table 3 S709 S710 S712 S713 S714 S715 S716 S717 S718 S719 S720 S711 S10 S11 S12 S1 S2 S3 S4 S5 S6 S7 S8 S/ G pins GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 GS=1 G328 G327 G326 G325 G324 G323 G322 G321 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 G310 G309 PD17-0 h00000 h00100 h00200 h00300 h00400 h00500 h00600 h00700 h00800 h00900 h00A 00 h00B00 h00C00 h00D00 h00E00 h00F00 h01000 h01100 h01200 h01300 PD17-0 h00001 h00101 h00201 h00301 h00401 h00501 h00601 h00701 h00801 h00901 h00A 01 h00B01 h00C01 h00D01 h00E01 h00F01 h01001 h01101 h01201 h01301 PD17-0 h00002 h00102 h00202 h00302 h00402 h00502 h00602 h00702 h00802 h00902 h00A 02 h00B02 h00C02 h00D02 h00E02 h00F02 h01002 h01102 h01202 h01302 S9 PD17-0 h00003 h00103 h00203 h00303 h00403 h00503 h00603 h00703 h00803 h00903 h00A 03 h00B03 h00C03 h00D03 h00E03 h00F03 h01003 h01103 h01203 h01303 PD17-0 h000EC h001EC h002EC h003EC h004EC h005EC h006EC h007EC h008EC h009EC h00A EC h00BE C h00CEC h00DEC h00EEC h00FEC h010EC h011EC h012EC h013EC PD17-0 h000ED h001ED h002ED h003ED h004ED h005ED h006ED h007ED h008ED h009ED h00A ED h00BE D h00CED h00DED h00EED h00FED h010ED h011ED h012ED h013ED PD17-0 h000EE h001EE h002EE h003EE h004EE h005EE h006EE h007EE h008EE h009EE h00A EE h00BE E h00CEE h00DEE h00EEE h00FEE h010EE h011EE h012EE h013EE PD17-0 h000EF h001EF h002EF h003EF h004EF h005EF h006EF h007EF h008EF h009EF h00A EF h00BE F h00CEF h00DEF h00EEF h00FEF h010EF h011EF h012EF h013EF G301 G302 G303 G304 G305 G306 G307 G308 G309 G310 G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 G28 G27 G26 G25 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 h12C00 h12D00 h12E00 h12F00 h13000 h13100 h13200 h13300 h13400 h13500 h13600 h13700 h13800 h13900 h13A 00 h13B00 h13C00 h13D00 h13E00 h13F00 h12C01 h12D01 h12E01 h12F01 h13001 h13101 h13201 h13301 h13401 h13501 h13601 h13701 h13801 h13901 h13A 01 h13B01 h13C01 h13D01 h13E01 h13F01 h12C02 h12D02 h12E02 h12F02 h13002 h13102 h13202 h13302 h13402 h13502 h13602 h13702 h13802 h13902 h13A 02 h13B02 h13C02 h13D02 h13E02 h13F02 h12C03 h12D03 h12E03 h12F03 h13003 h13103 h13203 h13303 h13403 h13503 h13603 h13703 h13803 h13903 h13A 03 h13B03 h13C03 h13D03 h13E03 h13F03 h12CEC h12DEC h12EEC h12FEC h130EC h131EC h132EC h133EC h134EC h135EC h136EC h137EC h138EC h139EC h13A EC h13BE C h13CEC h13DEC h13EEC h13FEC h12CED h12DED h12EED h12FED h130ED h131ED h132ED h133ED h134ED h135ED h136ED h137ED h138ED h139ED h13A ED h13BE D h13CED h13DED h13EED h13FED h12CEE h12DEE h12EEE h12FEE h130EE h131EE h132EE h133EE h134EE h135EE h136EE h137EE h138EE h139EE h13A EE h13BE E h13CEE h13DEE h13EEE h13FEE h12CEF h12DEF h12EEF h12FEF h130EF h131EF h132EF h133EF h134EF h135EF h136EF h137EF h138EF h139EF h13A EF h13BE F h13CEF h13DEF h13EEF h13FEF Rev.0.5, July.31.2003, page 24 of 196 HD66781 Relation between GRAM data and Display data (SS=0, BGR=0) Preliminary The following figure illustrates the relationship between data on GRAM and display data through each interface. 80 system 18-bit interface (1 transmission/pixel) GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(3n+1) S(3n+2) S(3n+3) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 16-bit interface (1 transmission/pixel) GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 G3 G2 B1 B0 Output pin S(3n+1) S(3n+2) S(3n+3) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 16-bit interface (2 transmissions/pixel) 1 1st transmission GRAM data 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 DB 16 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(3n+1) S(3n+2) S(3n+3) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 16-bit interface (2 transmissions/pixel) 2 1st transmission 2nd transmission GRAM data DB 2 DB 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(3n+1) S(3n+2) S(3n+3) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80-system 18/16-bit interface (SS = 0, BGR = 0) Rev.0.5, July.31.2003, page 25 of 196 HD66781 80 system 9-bit interface (2 transmissions/pixel) 1st transmission GRAM data 2nd transmission Preliminary DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(3n+1) S(3n+2) S(3n+3) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 8-bit interface (big endian) / SPI (2 transmissions/pixel) 1st transmission GRAM data 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 8-bit interface / (3 transmissions/pixel) 1 1st transmission 2nd transmission 3rd transmission GRAM data DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 8-bit interface / (3 transmissions/pixel) 2 1st transmission GRAM data 2nd transmission 3rd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 3: Upper 2-bit data of each transmission are not used. 80 system 8-bit interface (little endian) / (2 transmissions/pixel) 2nd transmission GRAM data 1st transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80-system 9/8-bit interface (SS = 0, BGR = 0) Rev.0.5, July.31.2003, page 26 of 196 HD66781 18 bit RGB interface (1 transmission/pixel) GRAM data Preliminary PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 16-bit RGB interface (1 transmission/pixel) GRAM data PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 6-bit RGB interface (3 transmissions/pixel) 1st transmission GRAM data 2nd transmission 3rd transmission PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(3n+1) S(3n+2) S(3n+3) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display RGB interface (SS = 0, BGR = 0) Rev.0.5, July.31.2003, page 27 of 196 HD66781 Relation between GRAM address and Screen position (SS=1, BGR=1) Table 4 S709 S710 S712 S713 S714 S715 Preliminary S716 S717 S718 S719 S/ G pins GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 GS=1 G328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 PD17-0 h000EF h001EF h002EF h003EF h004EF h005EF h006EF h007EF h008EF h009EF h00A EF h00BE F h00CEF h00DEF h00EEF h00FEF h010EF h011EF h012EF h013EF PD17-0 h000EE h001EE h002EE h003EE h004EE h005EE h006EE h007EE h008EE h009EE h00A EE h00BE E h00CEE h00DEE h00EEE h00FEE h010EE h011EE h012EE h013EE PD17-0 h000ED h001ED h002ED h003ED h004ED h005ED h006ED h007ED h008ED h009ED h00A ED h00BE D h00CED h00DED h00EED h00FED h010ED h011ED h012ED h013ED PD17-0 h000EC h001EC h002EC h003EC h004EC h005EC h006EC h007EC h008EC h009EC h00A EC h00BE C h00CEC h00DEC h00EEC h00FEC h010EC h011EC h012EC h013EC PD17-0 h00003 h00103 h00203 h00303 h00403 h00503 h00603 h00703 h00803 h00903 h00A 03 h00B03 h00C03 h00D03 h00E03 h00F03 h01003 h01103 h01203 h01303 PD17-0 h00002 h00102 h00202 h00302 h00402 h00502 h00602 h00702 h00802 h00902 h00A 02 h00B02 h00C02 h00D02 h00E02 h00F02 h01002 h01102 h01202 h01302 PD17-0 h00001 h00101 h00201 h00301 h00401 h00501 h00601 h00701 h00801 h00901 h00A 01 h00B01 h00C01 h00D01 h00E01 h00F01 h01001 h01101 h01201 h01301 PD17-0 h00000 h00100 h00200 h00300 h00400 h00500 h00600 h00700 h00800 h00900 h00A 00 h00B00 h00C00 h00D00 h00E00 h00F00 h01000 h01100 h01200 h01300 G301 G302 G303 G304 G305 G306 G307 G308 G309 G310 G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 G28 G27 G26 G25 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 h12CEF h12DEF h12EEF h12FEF h130EF h131EF h132EF h133EF h134EF h135EF h136EF h137EF h138EF h139EF h13A EF h13BE F h13CEF h13DEF h13EEF h13FEF h12CEE h12DEE h12EEE h12FEE h130EE h131EE h132EE h133EE h134EE h135EE h136EE h137EE h138EE h139EE h13A EE h13BE E h13CEE h13DEE h13EEE h13FEE h12CED h12DED h12EED h12FED h130ED h131ED h132ED h133ED h134ED h135ED h136ED h137ED h138ED h139ED h13A ED h13BE D h13CED h13DED h13EED h13FED h12CEC h12DEC h12EEC h12FEC h130EC h131EC h132EC h133EC h134EC h135EC h136EC h137EC h138EC h139EC h13A EC h13BE C h13CEC h13DEC h13EEC h13FEC h12C03 h12D03 h12E03 h12F03 h13003 h13103 h13203 h13303 h13403 h13503 h13603 h13703 h13803 h13903 h13A 03 h13B03 h13C03 h13D03 h13E03 h13F03 h12C02 h12D02 h12E02 h12F02 h13002 h13102 h13202 h13302 h13402 h13502 h13602 h13702 h13802 h13902 h13A 02 h13B02 h13C02 h13D02 h13E02 h13F02 h12C01 h12D01 h12E01 h12F01 h13001 h13101 h13201 h13301 h13401 h13501 h13601 h13701 h13801 h13901 h13A 01 h13B01 h13C01 h13D01 h13E01 h13F01 h12C00 h12D00 h12E00 h12F00 h13000 h13100 h13200 h13300 h13400 h13500 h13600 h13700 h13800 h13900 h13A 00 h13B00 h13C00 h13D00 h13E00 h13F00 Rev.0.5, July.31.2003, page 28 of 196 S720 S711 S10 S11 S12 S1 S2 S3 S4 S5 S6 S7 S8 S9 HD66781 Relation between GRAM data and Display data (SS=1, BGR=1) 80 system 18-bit interface (1 transmission/pixel) GRAM data Preliminary DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(720- 3n) S(719- 3n) S(718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 16-bit interface (1 transmission/pixel) DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM data RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 G3 G2 B1 B0 Output pin S(720- 3n) S(719 - 3n) S(718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 16 bit interface (2 transmissions/pixel) 1 1st transmission DB DB DB 8 11 10 2nd transmission GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 DB 16 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(720- 3n) S(719- 3n) S(718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 16 bit interface (2 transmissions/pixel) 2 1st transmission GRAM data DB 2 DB 1 DB 17 DB 16 2nd transmission DB DB DB DB 14 13 12 15 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(720- 3n) S(719- 3n) S(718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80-system18/16-bit interface (SS = 1, BGR = 1) Rev.0.5, July.31.2003, page 29 of 196 HD66781 80 system 9-bit interface (2 transmissions/pixel) 1st transmission GRAM data 2nd transmission Preliminary DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Output pin S(720 - 3n) S(719 - 3n) S(718 -3n) Note 1 : n = Lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 8-bit interface (big endian) / SPI (2 transmissions/pixel) 1st transmission GRAM data 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720- 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80 system 8-bit interface / (3 transmissions/pixel) 1 1st transmission 2nd transmission 3rd transmission GRAM data DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720- 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 80 system 8-bit interface / (3 transmissions/pixel) 2 1st transmission GRAM data 2nd transmission 3rd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720 - 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display Note 3 : Upper 2-bit data of each transmission are not used. 80 system 8-bit interface (little endian) / (2 transmissions/pixel) 2nd transmission GRAM data 1st tansmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720- 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 80-system 9/8-bit interface (SS = 1, BGR = 1) Rev.0.5, July.31.2003, page 30 of 196 HD66781 18 bit RGB interface (1 transmission/pixel) GRAM data Preliminary PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720 - 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display 16-bit RGB interface (1 transmission/pixel) GRAM data PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720 - 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 65,536 color display 6-bit RGB interface (3 transmissions/pixel) 1st transmission GRAM data 2nd transmission 3rd transmission PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 RGB Assignment Output pin R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S(720 - 3n) S(719 - 3n) S(718 - 3n) Note 1 : n = lower 8 bits of address (0 ~ 239) Note 2 : 262,144 color display RGB interface (SS = 1, BGR = 1) Rev.0.5, July.31.2003, page 31 of 196 HD66781 Preliminary Instruction Outline The HD66781 adapts an 18-bit bus architecture that enables high-speed interfacing with high-performance microcomputers. The HD66781 starts internal processing of 18/16/9/8/-bit data sent from external after storing control information in the instruction register (IR) and data register (DR). Since the internal operation of HD66781 is determined by signals sent from the microcomputer, register selection signal (RS), read/write signal (R/W), and internal 16-bit data bus signals (DB15 to DB0) are called instructions. GRAM is accessed through internal 18-bit data bus. The HD66781 has ten categories of instruction. 1. 2. 3. 4. Specify index Read status Control display Power management control 5. Graphics data processing 6. Set internal GRAM address 7. Transfer data to and from internal GRAM 8. Make an internal -adjustment 9. Control a panel 10. Control OSD display Normally, the instruction to write data on GRAM is used the most often. The address of internal GRAM is updated automatically after data are written to the internal GRAM. With window address function, this reduces the amount of data transmission to minimum and thereby lightens the load on the program processed by the microcomputer. Since instructions are executed in 0 cycle, it is possible to write instructions consecutively. Rev.0.5, July.31.2003, page 32 of 196 HD66781 Instruction data format Preliminary As the following figure shows, the assignment to the 16 instruction bits (IB15-0) varies according to the interface in use. An instruction must adopt the data format for each interface. 80 system 18-bit interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Instruction bit (IB) IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 80 system 16-bit interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction bit (IB) IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 80 system 9-bit interface 1st transmission 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 Instruction bit (IB) IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 80 system 8-bit interface (big endian) / SPI (2 transmisions) 1st transmission 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction bit (IB) IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 80 system 8-bit interface (little endian) / (2 transmisions) 2nd transmission 1st transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction bit (IB) IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 80-system interface instruction data format Rev.0.5, July.31.2003, page 33 of 196 HD66781 Preliminary Basic Operation modes The basic operation modes of HD66781 and transitions between the modes are illustrated as follows. A transition between the modes must be made according to the instruction setting flow. STB=1 Sleep mode STB=0(at SLP=1) Oscillation Start OSC =1 Stand-by release Standby mode Sleep release STB = 0 Standby release STB = 1 Standby set Sleep set Display OFF Initialization Reset state Reset Deep standby release flow DSTB = 1 Deep standby set Display OFF flow (Power OFF flow) Display ON flow (Power ON flow) Deep standby mode moving picture display VSYNC i/F flow 2 (DM=10, RM=0) VSYNC interface VSYNC i/F flow 1 (DM=00, RM=0) Internal clock display RGB i/F (1) flow 1 (DM=01, RM=1) RGB i/F (1) flow 2 (DM=00, RM=0) moving picture display RGB interface (1) System i/F access RGB i/F (2) flow 1 while displaying moving picture (DM=01, RM=0) RGB interface (2) RGB i/F(2) flow 2 (DM=01, RM=1) Partial display flow 2 Partial display flow 1 Partial Display Panel control Display color control 262k-color mode BASEE =0 OSDE =1 8 262k color flow OSD image display (partial display) 262k 8 color flow 262k Low power consumption display mode Base image display BASEE=1 OSDE=1 BASEE =1 OSDE =0 OSD display BASEE =1 OSDE =1 Base image display BASEE=1 OSDE =0 BASEE =0 OSDE =1 Low power consumption display mode 262k 8-color mode Low power consumption display mode Basic operation modes Rev.0.5, July.31.2003, page 34 of 196 HD66781 Instructions Preliminary The following are detail explanations of instructions with illustrations of instruction bits (IB15-0) assigned to each interface. Index/Status/Display control instruction Index (IR) R/W W RS 0 IB15 * IB14 IB13 IB12 IB11 * * * * IB10 ID10 IB9 ID9 IB8 ID8 IB7 ID7 IB6 ID6 IB5 ID5 IB4 ID4 IB3 ID3 IB2 ID2 IB1 ID1 IB0 ID0 The index instruction specifies the control register and the RAM control indexes that are accessed (R000h to R508h). The register number is set in binary from "000_0000_0000" to "101_0000_1000". Do not access to the registers and bits to which the index and the instruction bit are not assigned. Status read (SR) R/W R RS 0 IB15 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 L8 IB7 L7 IB6 L6 IB5 L5 IB4 L4 IB3 L3 IB2 L2 IB1 L1 IB0 L0 SR read the internal status of HD66781. L[8:0]: Indicate the position of the raster-row driving liquid crystal. Start Oscillation (R000h) R/W W R RS 1 1 IB15 * 0 IB14 * 0 IB13 * 0 IB12 * 0 IB11 * 0 IB10 * 1 IB9 * 1 IB8 * 1 IB7 * 1 IB6 * 0 IB5 * 0 IB4 * 0 IB3 * 0 IB2 * 1 IB1 * 0 IB0 1 0 The start oscillation instruction restarts the oscillator in a halt state during the standby mode. After executing this instruction, wait at least 10ms for stabilizing oscillation before issuing a next instruction. For details, see " Standby/Sleep mode" (p190.). The device code "0781"H is read out when this register is forced to read out. Rev.0.5, July.31.2003, page 35 of 196 HD66781 Driver Output Control (R001h) Preliminary R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 LT PS IB8 SS IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 IB1 0 IB0 0 0 0 0 LTPS: Select the type of a panel. The output waveforms from SFTCLK1, 2 vary according to the setting of the panel. When LTPS = 0, a-Si TFT panel waveforms are output. When LTPS = 1, low temperature poly-Si TFT panel waveforms are output. See SFTCLK waveforms (p.67) for detail. Make a setting for this register when D[1:0] = 2'h0. SS: Select the correspondence between RAM write address and source driver output. SS = "0": data written in H'00000 is output from S1. SS = "1": data written in H'00000 is output from S720. For details, see "GRAM Address Map". By making settings for both SS and RGB bits, the assignment of RGB dots to the S1 ~ S720 pins is determined. When SS = 0 and BGR = 0, R, G, B are assigned interchangeably in this order from S1 to S720. When SS = 1 and BGR =1, R, G, B are assigned interchangeably in this order from S720 to S1. Changes in the SS and BGR settings require RAM data rewrite. LCD Driving Wave Control (R002h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 FLD1 FLD0 B/C IB8 EOR IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 NW5 NW4 NW3 NW2 NW1 NW0 NW[5:0]: Specify "n", the number of raster-rows from 1 to 64, to alternate every n+1 raster-rows when Cpattern waveform is generated (B/C = 1). EOR: When EOR = 1, alternations occur by applying EOR (exclusive OR) operation to an odd/even frame select signal and an n-raster-row inversion signal while a C-pattern waveform is generated (B/C =1). This instruction is used when liquid crystal alternate drive is not available due to a combination of numbers of LCD raster-rows and the value of "n". For details, see "n-raster-row inversion Alternate drive"(p.174). B/C: When B/C =0, field alternating waveforms are generated. Alternation occurs every frame to drive liquid crystal. When B/C=1, alternation occurs every n raster-rows. For details, see the "n-raster-row Inversion alternating Drive" section. Rev.0.5, July.31.2003, page 36 of 196 HD66781 Preliminary FLD[1:0]: Specify the number of fields for n-field interlaced drive. For details, see the "Interlaced Drive"(p.175) section. Table 5 FLD [1:0] 2'h0 2'h1 2'h2 2'h3 Numbers of fields Setting disabled 1 field (= 1 frame) Setting disabled 3 fields Note 1) This instruction is not available with the external display interface. In the external display interface mode, make sure FLD[1:0] = 2'h1. The following functions are not available during interlaced drive (FLD =2'h3). Table 6 Unavailable functions when FLD = 2'h3 External display interface OSD function ( blending) Scroll function Resizing function (vertical direction magnification) Entry Mode 1 (R003h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 TRI DFM 0 IB8 0 IB7 0 IB6 0 IB5 IB4 IB3 AM IB2 0 IB1 IB0 BGR 0 0 HWM I/D1 I/D0 OSD ODF This instruction is for writing data from the microcomputer to the internal GRAM of HD66781. ODF: Set the format to write OSD data to the internal RAM. When ODF =0, assign transmission rate bits ( channel) to the LSB of RGB data. When ODF = 1, assign transmission rate bit ( channel) to the MSB. OSD bit must be "1" when writing OSD data. Rev.0.5, July.31.2003, page 37 of 196 HD66781 Table 7 OSD ODF 0 1 1 * 0 1 Preliminary BGR = 0 D17 R5 R5 2 D16 R4 R4 1 D15 R3 R3 0 D14 R2 R2 R4 D13 R1 R1 R3 D12 R0 2 R2 D11 G5 G5 R1 D10 G4 G4 R0 D9 G3 G3 G4 D8 G2 G2 G3 D7 G1 G1 G2 D6 G0 1 G1 D5 B5 B5 G0 D4 B4 B4 B4 D3 B3 B3 B3 D2 B2 B2 B2 D1 B1 B1 B1 D0 B0 0 B0 Table 8 OSD ODF 0 1 1 * 0 1 BGR =1 D17 B5 B5 0 D16 B4 B4 1 D15 B3 B3 2 D14 B2 B2 B4 D13 B1 B1 B3 D12 B0 0 B2 D11 G5 G5 B1 D10 G4 G4 B0 D9 G3 G3 G4 D8 G2 G2 G3 D7 G1 G1 G2 D6 G0 1 G1 D5 R5 R5 G0 D4 R4 R4 R4 D3 R3 R3 R3 D2 R2 R2 R2 D1 R1 R1 R1 D0 R0 2 R0 Table 9 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Transmission rate 0% 25% 75% 50% 100% Display screen Base picture display Setting disabled Base picture (75%) + OSD image (25%) display Base picture (25%) + OSD image (75%) display Base picture (50%) + OSD image (50%) display Setting disabled OSD image display Setting disabled OSD: Set RAM write data as OSD data. Set OSD =1, when writing OSD data. By setting OSD to 1, OSD data are written to the internal RAM according to the format set by ODF. OSD =0: Write normal picture data (18-bit RGB) to RAM OSD =1: Write OSD image data (18-bit (+RGB)) to RAM AM: Set the automatic updating method of address counter after data are written to GRAM. AM =0, the address counter is updated in horizontal direction. AM =1, the address counter is updated in vertical direction. When a window-address range is specified, data are written in the window-address range specified within the GRAM in accordance with I/D1-0 and AM setting. I/D[1:0]: I/D sets automatic increment (+1) and automatic decrement (-1) of address counter (AC) after data are written to GRAM. When I/D=0, the address counter is incremented or decremented in horizontal direction (lower address: AD7-0). When I/D =1, the address counter is incremented or decremented in vertical direction (upper address: AD16-8). The AM bit specifies the address transition direction when data are being written to GRAM. Rev.0.5, July.31.2003, page 38 of 196 HD66781 Preliminary HWM: When HWM =1, data are written to GRAM in high speed with low power consumption. In power saving high-speed write mode, the data in the horizontal line of rectangular area specified by the window address are stored in the line buffer and one-line data are written to GRAM at once. This minimizes the number of RAM access required to write data and thereby reduces power consumption. When HWM =1, the data write in horizontal direction must be executed by line of the specified windowaddress range. If data write is terminated in the middle of the line, data in that line are not correctly written to GRAM. Note 1) Insertion of dummy write is not required in high-speed write mode. Note 2) Data in the buffer will be erased if RAM write is terminated in the middle of a line and other instruction set is executed. Note 3) In the high-speed write mode, wait at least 2 write cycles (tcycw) of the normal write mode after RAM write before making a transition from RAM write to index write. BGR: Change the order of (R), (G), (B) dots to (B), (G), (R) when the dots are assigned to the 18-bit write data. BGR=0, the dot order (R), (G), (B) is not changed when 18-bit data are written to GRAM. BGR =1, the dot order changes from (R), (G), (B) to (B), (G), (R) when 18-bit data are written to GRAM. The assignment of bit of OSD data is also changed. DFM: Set the data format for 3-RAM-write 18-bit data transfers in 80-system 8-bit interface (big-endian) mode when IM3-0 = GND/GND/ Vcc1/Vcc1 in conjunction with TRI. DFM =0, RGB 18-bit data are written to GRAM by byte-boundary 3 transfers. DFM =1, RGB 18-bit data are written to GRAM by 3 x 6-bit transfer. Set the data format for 2-RAM-write 18-bit data transfers in 80-system 16-bit interface mode when IM3-0 = GND/GND/Vcc1/GND in conjunction with TRI. DFM =0, RGB 18-bit data are written to GRAM in the MSB format by 2 transfers. DFM =1, RGB 18-bit data are written to GRAM in the LSB format by 2 transfers. DFM must be set to 0, when not using 8- or16-bit interface. TRI: Make the 3-RAM-write transfers available in 80-system 8-bit interface (big-endian) when IM3-0 = GND/GND/Vcc1/Vcc1. TRI =0, 16-bit RAM data are transferred in 2 transfers. TRI =1, 18-bit RAM data are transferred in 3 transfers. Make the 2-RAM-write transfers available in 80-system 16-bit interface (big-endian) when IM3-0 = GND/GND/Vcc1/GND. TRI =0, 16-bit RAM data are transferred in one transfer. TRI =1, 18-bit RAM data are transferred in 2 transfers. TRI must be set to 0, when not using 8- or 16-bit interface. During RAM read, set TRI = 0. Rev.0.5, July.31.2003, page 39 of 196 HD66781 8-bit interface RAM write transmission formula IM3-0 = (GND, GND, Vcc1, Vcc1) 80 system 8-bit interface(big endian) (2 transmissions/pixel) 65,536 colors n 0 * GRAM data 1st transmission 2nd transmission Preliminary TRI DFM DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 IM3-0 = (GND, Vcc1, Vcc1, Vcc1) 80 system 8-bit interface (little endian) (2 transmissions/pixel) 65,536 colors n 0 * GRAM data 2nd transmission 1st transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 IM3-0 = (GND, GND, Vcc1, Vcc1) 80 system 8-bit interface (3 transmissions/pixel) 262,144 colors 1st transmission 2nd transmission 3rd transmission 1 0 GRAM data DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 IM3-0 = (GND, GND, Vcc1, Vcc1) 80 system 8-bit interface (3 transmissions/pixel) 262,144 colors 1st transmission 2nd transmission 3rd transmission 1 1 GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 8-bit interface: RAM write transmission Note 1) Instruction setting is transferred by 2 x 8-bit transmissions regardless of TRI and DFM settings. Rev.0.5, July.31.2003, page 40 of 196 HD66781 16-bit interface RAM write transmission formula 80 system 16-bit interface (1 transmission/pixel) 65,536 colors n Preliminary TRI DFM 0 * GRAM data 1st transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80 system 16 -bit interface (2 transmissions/pixel) 262,144 colors 1st transmission 2nd transmission 1 0 GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 DB 16 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80 system 16 -bit interface (2 transmissions/pixel) 262,144 colors 1 1 GRAM data 1st transmission 2nd transmission DB 2 DB 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 16-bit interface: RAM write transmission Note 1) Instruction setting is transferred by 1 x 16-bit transmission regardless of TRI and DFM settings. Direction Setting I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement 17'00000 I/D1-0 = "01" Horizontal: Increment Vertical: Decrement 17'00000 I/D1-0 = "10" Horizontal: Decrement Vertical: Increment 17'00000 I/D1-0 = "11" Horizontal: Increment Vertical: Increment 17'00000 AM = "0" Horizontal 17'h19FEF 17'00000 17'00000 17'h19FEF 17'00000 17'h19FEF 17'00000 17'h19FEF AM = "1" Vertical 17'h19FEF 17'h19FEF 17'h19FEF 17'h19FEF Address direction setting Note 1) When a window-address range is specified, write operation is executed only within the specified window-address range of GRAM. Rev.0.5, July.31.2003, page 41 of 196 HD66781 Resizing Control 1/2 (R004/R005h) R/W W W RS 1 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 RCV 1 RSE V1 IB8 IB7 IB6 0 0 IB5 IB4 IB3 0 0 IB2 0 0 Preliminary IB1 IB0 RCV 0 0 RSE V0 0 RCH1 RCH0 0 0 RSR1 RSR0 0 RSEH RSE RSE RSE RSE V7 V6 V5 V4 RSE RSE V3 V2 RSR[1:0]: Set the contraction scale which is applied during RAM write. When the resizing scale is set, data are written to RAM according to this bit scale in horizontal and vertical directions. See the "Resizing Function" (p.105) section for details. RCH[1:0]: RCH specifies the number of surplus pixels in the horizontal direction, which are made after resizing a picture. By specifying the number of surplus pixels, it is possible to disregard the surplus pixels when data are transferred. This instruction is only available with resizing function. Set RCH = 2'h0 when resizing function is not used (RSR = 2'h0). RCV[1:0]: RCV specifies the number of surplus pixels in the vertical direction, which are made after resizing a picture. By specifying the number of surplus pixels, it is possible to disregard the surplus pixels when data are transferred. This instruction is only available with resizing function. Set RCV = 2'h0 when resizing function is not used (RSR = 2'h0). RSEH: Set the magnifying scale in the horizontal direction of a picture. When the magnifying scale is set, data are written to RAM according to the bit scale in horizontal direction. See "Resizing Function" for details. RSEV[7:0]: Set magnifying scale in the vertical direction of a picture. When the magnifying scale is set, the data in the internal RAM are magnified when displayed. Note 1) When using picture magnification function, the picture resizing scale register (contraction) must be RSR1-0 = 2'h0. Note 2) When using picture contraction function, the picture resizing scale (magnification) must be set RSEV7-0 = 8'h00, RSEH = 0. Note 3) Base picture scrolling function and vertical-direction display magnification function cannot be used simultaneously. Settings for resizing scales Table 10 Resizing scale ratio setting (RSR) Resizing scale No resizing (x 1) x 1/2 Setting disabled x 1/4 RSR[1:0] 2'h0 2'h1 2'h2 2'h3 Rev.0.5, July.31.2003, page 42 of 196 HD66781 Table 11 Preliminary Setting for the number of surplus pixel in the horizontal/vertical direction (RCV, RCH) Number of pixel surplus in horizontal/vertical direction 0 pixel 1 pixel 2 pixels 3 pixels RCH [1:0] / RCV [1:0] 2'h0 2'h1 2'h2 2'h3 Note 1) 1 pixel = 1RGB Table 12 magnification in horizontal direction (RSEH) RSEH 2'h0 2'h1 Magnification No resizing (x1) 2 times (x2) Table 13 BASE picture magnification in the vertical direction (RSEV) Magnification No resizing (x1) 2 times (x2) Setting disabled Setting disabled RSEV [1:0] 2'h0 2'h1 2'h2 2'h3 Table 14 OSD image 1 magnification in the vertical direction (RSEV) Magnification No resizing (x1) 2 times (x2) 4 times (x4) Setting disabled RSEV [3:2] 2'h0 2'h1 2'h2 2'h3 Table 15 OSD image 2 magnification in the vertical direction (RSEV) Magnification No resizing (x1) 2 times (x2) 4 times (x4) Setting disabled RSEV [5:4] 2'h0 2'h1 2'h2 2'h3 Rev.0.5, July.31.2003, page 43 of 196 HD66781 Table 16 OSD image 3 magnification in the vertical direction (RSEV) Magnification No resizing (x1) 2 times (x2) 4 times (x4) Setting disabled Preliminary RSEV [7:6] 2'h0 2'h1 2'h2 2'h3 Display Control 1 (R007h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 OSD OSD OSD E2 E1 E0 0 0 0 IB8 BASE E IB7 0 IB6 0 IB5 0 IB4 DTE IB3 0 IB2 0 IB1 D1 IB0 D0 D[1:0]: The graphics display is shown when D[1] = 1, and turned off when D[1] = 0. When setting D[1] = 0, the data are retained in GRAM. This means the graphics display is instantly shown when setting D[1] to 1. When D[1] is 0 (i.e. the display is not shown) all source outputs are set to the GND level. This reduces the charged/discharged current on LCD, which is generated during liquid crystal alternate drive. When D= 2'b01, the display operation is being executed inside the HD66781 even while the external display is turned off. When D = 2'b00, both internal and external display operations are halted. In combination with GON and DTE bits, D1-0 bits control ON/OFF of display. For details, see the "Instruction Setting"(p.185) section. Table 17 D[1:0] 2'h0 2'h1 2'h2 2'h3 Source output GND GND Non-lit display Display HD66781 internal operation Halt Continue Continue Continue Gate control signal/Power supply IC, LCD panel control signal (FLM, CL1/SFTCLK1, 2, DCCLK, EQ) Halt Continue Continue Continue Note 1) Data from the microcomputer can be written to GRAM irrespective of D bit setting. Note 2) D = 2'h00 during the standby mode. In this case, the register setting of D bit is not changed. Note 3) A picture displayed when D = 2'b11 is specified by the BASEE setting. Rev.0.5, July.31.2003, page 44 of 196 HD66781 DTE: Control the DISPTMG output. Table 18 DTE 0 1 DISPTMG GND Vcc1/GND Preliminary BASEE: Set display enable of a base image. The D-bit setting takes precedence over the BASEE-bit setting. Table 19 D[1:0] 2'h0 2'h1 2'h2 2'h3 BASEE * * * 0 1 Source Output (S1~S720) GND GND Non-lit level Non-lit display Display BASE image Note 1) The source output at the "non-lit display" level is determined according to the PTS bit setting. Note 2) Gate lines are scanned in the manner determined by the PTS bit setting during the non-lit display. OSDE0: Display enable bit for OSD image 1. OSDE1: Display enable bit for OSD image 2. OSDE2: Display enable bit for OSD image 3. OSDE0/OSDE1/OSDE2 = 0, the HD66781 does not display OSD images. Only base images are displayed. OSDE0/OSDE1/OSDE2 = 1, the HD66781 displays OSD images according to the channel bits in the pixel data of the OSD image. When OSDE =1, while a base image is not displayed (BASEE =0), an OSD is displayed with 100% transmission rate. Rev.0.5, July.31.2003, page 45 of 196 HD66781 Display Control 2 (R008h) Preliminary R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 FP3 FP2 FP1 IB8 FP0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 BP3 IB2 BP2 IB1 BP1 IB0 BP0 FP [3:0]: Set the number of lines for a front porch (a blank period made before the end of display). BP [3:0]: Set the number of lines for a back porch (a blank period made after the beginning of display). In the external display interface mode, a back porch (BP) period starts at the falling edge of VSYNC and display operation starts after the back porch period. A front porch (FP) period starts after the numbers of raster-rows set with NL bit are driven for display. After the front porch period, a blank period continues until the next VSYNC input. Table 20 VSYNC FP [3:0] BP [3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Number of Front porch line Number of Back porch line Setting disabled Setting disabled 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines Setting disabled Back porch Display Area Front porch Note: The output timing to the LCD panel is delayed by 2 lines in relation to the input-synchronizing signal Set BP, FP, and MP within the range indicated below. Table 21 Internal clock operation RGB interface VSYNC interface FLD = 2'h1 FLD = 2'h3 BP 2 lines BP = 3 lines BP 2 lines BP 2 lines FP 2 lines FP = 5 lines FP 2 lines FP 2 lines FP+BP 16 lines FP+BP = 16 lines FP+BP 16 lines Rev.0.5, July.31.2003, page 46 of 196 HD66781 Display Control 3 (R009h) Preliminary R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 IB8 IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 PTS2 PTS1 PTS0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0 ISC [3:0]: Specify the cycle to scan gate lines, when PTG bits set the scan mode in the non-display area to the interval scan mode. The scan cycle is always odd number of frames, and polarity inversion is applied each timing when gate lines are scanned. Table 22 ISC [3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Scan cycle Setting disabled 3 frames 5 frames 7 frames 9 frames 11 frames 13 frames 15 frames 17 frames 19 frames 21 frames 23 frames 25 frames 27 frames 29 frames 31 frames When (fFLM) = 60Hz 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ns 317ms 351ms 384ms 418ms 451ms 484ms 518ms PTG [1:0]: Set the DISPTMG output to determine the gate bus line scan mode in non-display area. The setting is applied to all no-display areas and front/back porch periods of the entire panel. Table 23 PTG[1:0] 2'h0 2'h1 2'h2 2'h3 DISPTMG output Normal drive GND Interval drive Setting disabled Gate output in nondisplay area Normal scan VGL (fixed) Interval scan Source output in nondisplay area PT setting PT setting PT setting - Note 1) Set alternating drive to frame cycle when using interval scan. Rev.0.5, July.31.2003, page 47 of 196 HD66781 Preliminary PTS [2:0]: Determine the kind of source outputs in the no-display area, which is applied to the front/back porch periods and non-display area of partial display. When PTS [2] =1, the grayscale voltage generating amplifiers are halted except those for the V0 and V63 levels during no-display area drive period to reduce power consumption. Table 24 Non-display source output PTS[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Positive polarity V63 Setting disabled GND Hi-Z V63 Setting disabled GND Hi-z Negative polarity V0 Setting disabled GND Hi-Z V0 Setting disabled GND Hi-z Non-display area Operation of grayscale amplifier V0 to V63 V0 to V63 V0 to V63 V0, V63 V0, V63 V0, V63 Non-display area Step up clock frequency DC0, DC1 setting DC0, DC1 setting DC0, DC1 setting DC0, DC1 setting DC0, DC1 setting x 1/2 DC0, DC1 setting x 1/2 DC0, DC1 setting x 1/2 Note 1) Gate outputs in non-display area are controlled by the off-scan mode (PTG). Note 2) Grayscale amplifier operation halt and slowdown of step-up clocks are applied to the non-display area. Note 3) When DC[4:3]=2'h3, the frequency of step-up clocks in the non-display area are not slowed down half even if PTS[2:0] is set to 4, 6 or 7. Rev.0.5, July.31.2003, page 48 of 196 HD66781 Display Control 4 (R00Bh) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 FRC D16 ON B 0 0 0 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 IB0 COL COL 1 0 FRCON: Make a setting for the FRC mode. Control on and off of the FRC mode. D16B: When FRCON=1, the FRC mode sets in. When COL[1:0]=2'h1 and the low-power display mode, where only 32 operational amplifiers are used, the FRC mode enables display with abundant colors. For details, see "low-power display mode"(p.169). Set D16B to 1 when using a 16-bit interface (one-transfer 16-bit interface, 2-transfer 8-bit interface, 16-bit SPI, RGB interfaces). Table 25 Interface mode 18-bit, 16-bit x2, 9-bit x2, 8-bit x3, RGB 18-bit, 6-bit x3 16-bit x1, 8-bit x2, SPI FRCON 0 1 0 1 D16B * 0 * 1 Colors 262,144 250,047 65,536 64,512 Note 1) When the FRC mode is on, do not switch the interface mode settings (M, TRI, D16B registers) Note 2) When the FRC mode is on, 18-bit format data and 16-bit format data are not displayed simultaneously. COL[1:0]: When COL=2'h1, 32 grayscale operational amplifiers are halted. When making a setting, it must follow the setting sequence in the "Low Power Consumption Display Mode" section. When COL = 2'h2, 8-color mode sets in. When making a setting, it must follow the setting sequence in the "8-Color Display Mode" section. All operational amplifiers except V0 and V63 levels are halted for low power consumption display. Table 26 COL[1:0] 2'h0 2'h1 2'h2 2'h3 Amplifiers in operation 64 32 2 Setting disabled Available colors for display FRCON = 0 262,144 colors/65,536 colors 32,768 colors 8 colors Setting disabled FRCON = 1 250,047 colors/64,512 colors Setting disabled Note 1) When COL[1:0] =2'h1 and FRCON = 0, do not write data that correspond to the grayscale levels the amplifiers of which are halted. Rev.0.5, July.31.2003, page 49 of 196 HD66781 Table 27 amplifier V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Preliminary grayscale level amplifiers in operation (when REV=0) COL[1:0] 2'h0 2'h1 2'h2 GRAM data RGB 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F 6'h3F 6'h3E 6'h3D 6'h3C 6'h3B 6'h3A 6'h39 6'h38 6'h37 6'h36 6'h35 6'h34 6'h33 6'h32 6'h31 6'h30 6'h2F 6'h2E 6'h2D 6'h2C 6'h2B 6'h2A 6'h29 6'h28 6'h27 6'h26 6'h25 6'h24 6'h23 6'h22 6'h21 6'h20 amplifier V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 COL[1:0] 2'h0 2'h1 2'h2 GRAM data RGB 6'h20 6'h1F 6'h1E 6'h1D 6'h1C 6'h1B 6'h1A 6'h19 6'h18 6'h17 6'h16 6'h15 6'h14 6'h13 6'h12 6'h11 6'h10 6'h0F 6'h0E 6'h0D 6'h0C 6'h0B 6'h0A 6'h09 6'h08 6'h07 6'h06 6'h05 6'h04 6'h03 6'h02 6'h01 6'h00 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F *: amplifier in operation Rev.0.5, July.31.2003, page 50 of 196 HD66781 External Display interface Control 1 (R00Ch) R/W W RS 1 IB15 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 RM IB7 0 IB6 0 IB5 DM [1] IB4 DM [0] IB3 0 Preliminary IB2 0 IB1 RIM [1] IB0 RIM [0] RIM[1:0] Make settings for the RGB interface mode when the RGB interface is selected with DM and RM bits. The setting must be made before the display through an external display interface. Do not make changes to the setting during display. Table 28 RIM[1:0] 2'h0 2'h1 2'h2 2'h3 RGB interface mode 18-bit RGB interface (1 transmission/pixel) 16-bit RGB interface (1 transmission/pixel) 6-bit RGB interface (3 transmission/pixel) Setting disabled Colors 262,144 65,536 262,144 - Note 1) The instruction register setting is made only through a system interface. Note 2) Data transfer and DOTCLK input must be by the RGB unit when a 6-bit RGB interface is selected. DM[1:0]: Set a display operation mode. An interface for display operation is selected by the DM setting. DM allows switching between the internal clock operation mode and the external display interface mode. Do not try to switch between the external interface modes (RGB-I/F and VSYNC-I/F). Table 29 DM[1:0] 2'h0 2'h1 2'h2 2'h3 Display operation interface Internal clock operation RGB interface VSYNC interface Setting disabled- RM: Set a RAM access interface. RAM access is made only through the interface specified by the RM setting. Set RM to 1 when writing display data through the RGB interface. This setting is valid irrespective of the display operation mode. Changes in display data can be made by setting RM to 0, which enables RAM data overwrite through a system interface, even while the screens are displayed through the RGB interface mode. Table 30 RM 0 1 Display operation interface Internal clock operation/VSYNC interface RGB interface Rev.0.5, July.31.2003, page 51 of 196 HD66781 Preliminary As the following table shows, an optimum interface is selected for the kind of display by the external display interface control setting. Write display data during moving picture display (through RGB and VSYNC interfaces) in the high-speed write mode (HWM=1), which enables high-speed RAM access with low power consumption. Table 31 Kind of Display still picture moving picture Write over still picture area during moving picture display moving picture Operation mode internal clock operation only RGB interface (1) RGB interface (2) VSYNC interface RAM access setting (RM) system interface (RM = 0) RGB interface (RM = 1) system interface (RM = 0) system interface (RM = 0) Display operation mode (DM) internal clock operation (DM = 2'h0) RGB interface (DM = 2'h1) RGB interface (DM = 2'h1) VSYNC interface (DM = 2'h2) Note 1) The instruction register settings are made only through a system interface. Note 2) No switching between the RGB and VSYNC interfaces is made. Note 3) No change in the settings of RGB interface mode (RIM) is made during the RGB interface operation. Note 4) See "External Display Interface" for reference to the transition flows between the modes. Note 5) Use the RGB and VSYNC interfaces in the high-speed write mode (HWM =1). Internal clock mode: All display operations are controlled by signals generated by the internal clock in internal clock operation mode. All inputs through the external display interface are invalid. The internal RAM is accessible only through a system interface. RGB interface mode (1): Display operation is controlled by the frame synchronizing clock (VSYNC), line synchronizing signal (VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must be supplied throughout the display operation in this mode. All display data are stored in the internal RAM, transmitted through DB17-0 bits by pixel. The combination with the window address function enables simultaneous display of both moving picture areas and the internal RAM area. The data are transmitted only when the screen is being updated, thereby reducing the overall data transmission to minimum. The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to the frame synchronizing signal (VSYNC). Transmit pixel data through DB17-0 bits in accordance with the aforementioned setting. RGB interface mode (2): When RGB-I/F is selected, RAM data are changeable through the system interface. This write operation must be performed while display data are not being transmitted through the RGB-I/F (ENABLE = High). When reverting from the system interface mode to the data transmission through the RGB interface, make a new setting for the address set and index (R202h) after changing the aforementioned settings. Rev.0.5, July.31.2003, page 52 of 196 HD66781 Preliminary VSYNC interface mode: The internal display operation is synchronized with the frame-synchronizing signal (VSYNC) in the VSYNC interface mode. By writing data to RAM at a fixed speed on the falling edge of VSYNC, it enables moving pictures display with a system interface. In this case, there are some constraints in the RAM write speed and methods. For details, see "External Display Interface" (p.139). In the VSYNC-I/F mode, only VSYNC input is valid. Other input signals for the external display interface are invalid. The front porch (FP), back porch (BP) periods and display period (NL) are automatically generated in accordance to the frame synchronizing signal (VSYNC) according to the register setting of HD66781. Rev.0.5, July.31.2003, page 53 of 196 HD66781 Frame Cycle Control (R00Dh) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 IB8 IB7 0 IB6 0 IB5 0 IB4 IB3 IB2 Preliminary IB1 IB0 DIVI1 DIVI0 RTNI RTNI RTNI RTNI RTNI 4 3 2 1 0 RTNI[4:0]: Set IH (line) period. DIVI[1:0]: Set the division ratio of clocks for internal operations (DIV1-0). The internal operations are executed by the clocks, the frequency of which is divided according to the DIV1-0 setting. When changing the number of raster-rows to drive, adjust the frame frequency too. For details, see "Frame Frequency Adjustment Function"(p.178). Table 32 RTNI[3:0] 5'h00 : 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F clocks per line Setting disabled : Setting disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks DIVI[1:0] 2'h0 2'h1 2'h2 2'h3 division ratio 1/1 1/2 1/4 1/8 internal operation clock frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8 Note 1) fosc : R-C oscillation frequency Formula for frame frequency frame frequency = fosc : R-C oscillation frequency Line : Number of drive raster-rows (NL bit) division ration : DIVI bit clocks per line : RTNI bit fosc Number of clock per line x division ratio x (Line +FP+BP) [Hz] Rev.0.5, July.31.2003, page 54 of 196 HD66781 External Display Interface Control 2 (R00Eh) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 DIVE DIVE 0 0 0 0 0 0 0 1 0 Preliminary IB6 IB5 IB4 IB3 IB2 IB1 IB0 RTNE RTNE RTNE RTNERTNE RTNE RTNE 6 5 4 3 2 1 0 RTNE[6:0]: Specify the number of clocks for internal operation per 1H (line). Set the value of the number of DOTCLK input in 1H period, divided by the division ratio. DIVE[1:0]: Set the internal division ratio of DOTCLK (DIVE). The internal operation is executed according to the clocks divided by the division ratio set by DIVE. Table 33 RTNE[6:0] 7'h00 : 7'h0F 7'h10 7'h11 7'h12 : 7'h7D 7'h7E 7'h7F Clocks per line Setting disabled : Setting disabled 16 clocks 17 clocks 18 clocks : 125 clocks 126 clocks 127 clocks DIVE[1:0] Division Internal operation clock frequency 2'h0 Setting disabled 2'h1 1/4 fdotclk / 4 2'h2 1/8 fdotclk / 8 2'h3 1/16 fdotclk / 16 fdotclk: DOTCLK frequency External Display Interface Control 3 (R00Fh) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 IB3 IB2 IB1 IB0 VSPL HSPL 0 EPL DPL DPL: Specify the polarities of signals on DOTCLK pin. DPL=0: Input data on a rising edge of DOTCLK. DPL=1: Input data on a falling edge of DOTCLK. EPL: Specify the polarities of signals on ENABLE pin. EDL = 0 EDL = 1 Data are written to PD17 to PD 0 when ENABLE = 0. No data are written when ENABLE = 1. Data are written to PD17 to PD 0 when ENABLE = 1. No data are written when ENABLE = 0. Rev.0.5, July.31.2003, page 55 of 196 HD66781 HSPL: Specify the polarities of signals on HSYNC pin. HSPL=0: Low active. HSPL=1: High active. VSPL: Specify the polarities of signals on VSYNC pin. VSPL=0: Low active. VSPL=1: High active. Preliminary Gate Driver/LTPS LCD Panel Interface Control 1 (R010h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 FWI FWI 4 3 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 IB1 IB0 FWI FWI FWI 2 1 0 FTI2 FTI1 FTI0 FTI[2:0]: FTI bits specify the rising position of FLM during display operation with internal clocks (DM = 2'h0 or 2'h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the rising position of FLM is at a reference point. FWI[4:0]: FWI bits specifies the width of "High" of FLM during display operation with internal clocks (DM = 2'h0 or 2'h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the width of "High" of FLM is 1H. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 34 FTI[2:0] 2'h0 2'h1 2'h2 2'h3 FLM Rising position 0 clock 1 clock 2 clocks 3 clocks FWI[4:0] 5'h00 5'h01 5'h02 5'h03 : 5'h1D 5'h1E 5'h1F 29 clocks 30 clocks 31 clocks FLM "High" width 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are measured from the reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 56 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 2 (R011h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 SWI SWI 4 3 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 IB0 SWI SWI SWI 2 1 0 STI1 STI0 STI[1:0]: STI bits specifies the rising position of SFTCLK1/2 during display operation with internal clocks (DM = 2'h0 or 2'h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the rising position of CL1 is 8 clocks away from a reference point. SWI[4:0]: SWI bits specifies the width of "High" of SFTCLK1/2 during display operation with internal clocks (DM = 2'h0 or 2'h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 35 STI[1:0] 2'h0 2'h1 2'h2 2'h3 CL1/SFTCLK1, 2 Rising position 0 clock 1 clock 2 clocks 3 clocks SWI[4:0] 5'h00 5'h01 5'h02 5'h03 : 5'h1D 5'h1E 5'h1F 29 clocks 30 clocks 31 clocks CL1/SFTCLK1, 2 "High" width 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 57 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 3 (R012h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 IB0 SDTI SDTI 1 0 SDTI[1:0]: Specify the delay from a reference point of the source output during display operation with internal clocks (DM = 2'h0 or 2'h2). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 36 SDTI[1:0] 2'h0 2'h1 2'h2 2'h3 Source output delay 1 clock 2 clocks 3 clocks 4 clocks Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 58 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 4 (R013h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 IB8 IB7 DPW DPW DPW DPW DPW 0 I0 I4 I3 I2 I1 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 IB0 DPTI DPTI 1 0 DPTI[1:0]: Specify the rising position of DISPTMG during display operation with internal clocks (DM = 2'h0 or 2'h2). DPWI[4:0]: DPWI bits specifies the width of "High" of DISPTMG during display operation with internal clocks (DM = 2'h0 or 2'h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 37 DPTI[1:0] 2'h0 2'h1 2'h2 2'h3 DISPTMG Rising position 0 clock 1 clock 2 clocks 3 clocks DPWI[4:0] DISPTMG "High" width 5'h00 5'h01 5'h02 5'h03 : 5'h1D 5'h1E 5'h1F 29 clocks 30 clocks 31 clocks 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Note 2) The gate non-overlap period can be set to 0 when DPTI = "2'h0" and DPWI is set to the number of clocks more than that of the 1H period. Rev.0.5, July.31.2003, page 59 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 5 (R015h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 0 IB0 0 EQW EQW I1 I0 EQWI[1:0]: Specify the width of "High" of EQ during display operation with internal clocks (DM = 2'h0 or 2'h2). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Also see "Equalizing Function" for details on equalization. Table 38 EQWI[1:0] EQ "High" width 2'h0 2'h1 2'h2 2'h3 0 clock 1 clock 2 clocks 3 clocks Note 1) The clocks in the tables are measured from the source output alternating point. Rev.0.5, July.31.2003, page 60 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 6 (R016h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 FWE FWE FWE 5 4 3 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 Preliminary IB1 IB0 FWE FWE FWE 2 1 0 FTE2 FTE1 FTE0 FTE[2:0]: FTE bits specifies the rising position of FLM during display operation with DOTCLK (DM = 2'h1) when LTPS = 1. The setting of this register setting is invalid when LTPS = 0. In this case, the rising position of FLM is at a reference point. FWE[5:0]: FWE bits specifies the width of "High" of FLM during display operation with DOTCLK (DM = 2'h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the width of "High" of FLM is 1H. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 39 FTE[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 FLM Rising position 0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks FWE[5:0] 6'h00 6'h01 6'h02 6'h03 : 6'h3D 6'h3E 6'h3F 61 clocks 62 clocks 63 clocks FLM "High" width 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 61 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 7 (R017h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 SWE SWE SWE 5 4 3 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 Preliminary IB1 IB0 SWE SWE SWE 2 1 0 STE2 STE1 STE0 STE[2:0]: STE bits specifies the rising position of SFTCLK1/2 during display operation with DOTCLK (DM = 2'h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the rising position of CL1 is 8 clocks away from a reference point. SWE[5:0]: SWE bits specifies the width of "High" of SFTCLK1/2 during display operation with DOTCLK (DM = 2'h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 40 STE[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 CL1/SFTCLK1,2 Rising position 0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks SWE[5:0] CL1/SFTCLK1,2 "High" width 6'h00 6'h01 6'h02 6'h03 : 6'h3D 6'h3E 6'h3F 61 clocks 62 clocks 63 clocks 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 62 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 8 (R018h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 Preliminary IB2 IB1 IB0 SDTE SDTE SDTE 2 1 0 SDTE[2:0]: Specify the delay from a reference point of the source output during display operation with DOTCLK (DM = 2'h1). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 41 SDTE[2:0] Source output delay 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Setting disabled Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Rev.0.5, July.31.2003, page 63 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 9 (R019h) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 DPW DPW DPW DPW DPW DPW 0 0 0 E5 E4 E3 E2 E1 E0 IB6 0 IB5 0 IB4 0 IB3 0 Preliminary IB2 IB1 IB0 DPTE DPTE DPTE 2 1 0 DPTE[2:0]: Specify the rising position of DISPTMG during display operation with DOTCLK (DM = 2'h1). DPWE[5:0]: DPWE specifies the width of "High" of DISPTMG during display operation with DOTCLK (DM = 2'h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the falling position of CL1 is at a reference point. See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Table 42 DPTE[2:0] DISPTMG Rising position 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 6'h3E 6'h3F DPWE[5:0] DISPTMG "High" width 6'h00 6'h01 6'h02 6'h03 : 6'h3D 61 clocks 62 clocks 63 clocks 0 clock 1 clock 2 clocks 3 clocks : Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is set to 0 clock. Note 2) The gate non-overlap period can be set to 0 when DPTI = "2'h0" and DPWI is set to the number of clocks more than that of the 1H period. Rev.0.5, July.31.2003, page 64 of 196 HD66781 Gate Driver/LTPS LCD Panel Interface Control 10 (R01Bh) R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 EQW EQW EQW 0 0 0 0 0 0 E2 E1 E0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 Preliminary IB1 0 IB0 0 EQWE[2:0]: Specify the width of "High" of EQ DISPTMG during display operation with DOTCLK (DM = 2'h1). See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD panel interface are controlled by these settings. Also see "Equalizing Function" for details on equalization. Table 43 EQWE[2:0] EQ "High" width 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from the source output change. Rev.0.5, July.31.2003, page 65 of 196 HD66781 Reference point Preliminary FLM 1H period 8 clocks CL1 1H period M (Vcom) Equalization period (EQW) EQ DPT DISPTMG G1 G2 gate non-overlap period Sn Source output delay (SDT) Note: The figure shows waveforms for 1-line inversion AC drive. Output waveforms of a-Si TFT panel (LTPS = 0) Rev.0.5, July.31.2003, page 66 of 196 HD66781 Reference point Preliminary FLM FT FW 1H period ST 1H period SFTCLK1 SW ST SFTCLK2 SW M (Vcom) Equalization period (EWQ) EQ DPT DISPTMG Sn Source output delay (SDT) Note: The figure shows waveforms for 1-line inversion AC drive. Output waveforms of low-temperature poly-Si TFT panel (LTPS = 1) Rev.0.5, July.31.2003, page 67 of 196 HD66781 Power control 1 (R100h) R/W W RS 1 IB15 DC 4 IB14 DC 3 IB13 0 IB12 0 IB11 0 IB10 SAP 2 IB9 SAP 1 IB8 SAP 0 IB7 0 IB6 AP 2 IB5 AP 1 IB4 AP 0 IB3 0 Preliminary IB2 DS TB IB1 SLP IB0 STB STB: When STB = 1, the HD66781 enters into the standby mode. In the standby mode, display operation is completely halted, and all internal operations including the internal R-C oscillator and reception of external clock pulse, are halted. Only instructions to release from the standby mode (STB = 0) and to start oscillation are accepted during the standby mode. In the standby mode, a serial transfer to the gate driver/power supply IC cannot be made and it requires retransfer after release from the standby mode. Also in the standby mode, any change in the GRAM data or instruction setting cannot be made, but GRAM data are retained. SLP: When SLP = 1, the HD66781 enters into the sleep mode. In the sleep mode, internal display operation is halted except the R-C oscillator to reduce current consumption. No change is made to the GRAM data or instructions during the sleep mode, and the GRAM data and the instructions are retained. DSTB: When DSTB = 1, the HD66781 enters into the deep standby mode, where the power supply for the internal logic is turned off to save more power than the standby mode. The GRAM data and the instruction setting are destroyed in the deep standby mode and it requires resetting after release from the deep standby mode. Also in the deep standby mode, a serial transfer to the gate driver cannot be made and it requires a retransfer after the release from the deep standby mode. AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = "3'h0" to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. Also if AP[2:0] is set to other than 0, the clock for the step-up circuit DCCLK is output. SAP[2:0]: Adjust the amount of constant current in the operational amplifier of source driver. When the amount of constant current is set large, the liquid crystal drive capacity is enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set SAP[2:0] = "3'h0" to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. DC[4:3]: Select the frequency of clocks for the step-up circuit (DCCLK). If the DCCLK frequency is set high, display quality is enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. Rev.0.5, July.31.2003, page 68 of 196 HD66781 Preliminary Note: The AP[2:0] in the above description is the instruction bits for gate driver/power supply IC. The instruction setting in the AP[2:0] must be transferred to the gate driver/power supply IC before an instruction is executed. For details, see "Gate driver/power supply IC Serial Transfer". Table 44 SAP setting Current in the operational amplifier operation halt : op-amp, step-up circuit op-amp constant current flow rate : 0.65 op-amp constant current flow rate : 0.80 op-amp constant current flow rate : 1.00 op-amp constant current flow rate : 1.35 op-amp constant current flow rate : 1.60 Setting disabled Setting disabled DC setting DC[4:3] 2'h0 2'h1 2'h2 2'h3 DCCLK frequency SAP[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Fosc / 4 fosc / 8 fosc / 16 fosc / 32 Note 1) The amount of current in the above table is shown as a ratio against that of SAP[2:0] = 3'h3 as 1. Rev.0.5, July.31.2003, page 69 of 196 HD66781 Gate Driver/ Power Supply IC Interface Control 1 (R110h) R/W W R RS 1 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 TE TE IB7 0 0 IB6 0 0 IB5 0 0 IB4 0 0 IB3 0 0 Preliminary IB2 IDX 2 IDX 2 IB1 IDX 1 IDX 1 IB0 IDX 0 IDX 0 Gate Driver/ Power Supply IC Interface Control 2 (R111h) R/W W RS 1 IB15 0 IB14 0 IB13 0 IB12 TB 12 IB11 TB 11 IB10 TB 10 IB9 TB 9 IB8 TB 8 IB7 TB 7 IB6 TB 6 IB5 TB 5 IB4 TB 4 IB3 TB 3 IB2 TB 2 IB1 TB 1 IB0 TB 0 IDX[2:0]: The index register of the instruction, which is transferred to the gate driver/power supply IC. The instruction that corresponds to the index as determined by the IDX[2:0] setting is transferred to the gate driver or power supply IC through a serial interface for the gate/power supply IC. The following figures illustrates the bit array with which instructions are transferred. The upper 3 bits in the figures corresponds to the IDX[2:0] bits. The instructions of the indexes determined by the IDX[2:0]settings as below are transferred to the gate driver/power supply IC. When any change will be made to the instruction setting to the gate driver/power supply IC, the setting must be made first in the R111h register of HD 66781 before making a setting for IDX[2:0]. The transfer start (TE = 1) starts transferring the instructions, which is then followed by the execution. TE: The ENABLE for the serial transfer to the gate driver/power supply IC. TE=0 enables a serial transfer. TE=1 starts a transfer to the gate driver/power supply IC. When the transfer is completed, TE=0 is returned. A serial transfer takes 18 clocks at maximum (with reference to internal clocks). Do not make any changes to the instructions that are being transferred. Other instructions can be executable even during the instruction transfer. Note 1) The transfer of the NL[5:0], AP[2:0], FLD[1:0] settings to the gate driver/power supply IC must be made right after the instruction setting of HD66781. Make a same setting to the HD66781 and HD66783/HD667P21 with regard to NL, AP, FLD registers. Otherwise, a proper operation is not guaranteed. Note 2) As in the following figures, the bits to which no register is assigned must be overwritten with "0" or "1". Rev.0.5, July.31.2003, page 70 of 196 HD66781 HD66783 Instructions IDX2 0 0 0 0 1 1 1 1 IDX1 0 0 1 1 0 0 1 1 IDX0 TB12 TB11 TB10 TB9 TB8 TB7 VCO 0 0 GON BT[2] BT[1] BT[0] MG 1 0 1 0 1 0 1 GS 0 NL [5] 0 NL [4] 0 NL [3] 0 NL [2] 0 0 DC1 [2] DK DC1 [1] 1 DC1 [0] EQM VDV [4] 0 VDV [3] Preliminary TB6 TB5 TB4 TB3 TB2 TB1 TB0 DC0 DC0 DC0 AP AP AP 0 [2] [1] [0] [2] [1] [0] VRH VRH VRH VRH VC VC VC PON [0] [3] [2] [1] [0] [2] [1] VDV VDV VDV VCM VCM VCM VCM VCM [0] [2] [1] [0] [4] [3] [2] [1] Setting disabled Setting disabled Setting disabled SC SC SC SC SC SC NL NL N N N N N N [1] [0] [5] [4] [3] [2] [1] [0] NL NL 0 0 0 0 0 0 [0] [1] HD667P21 Instructions IDX2 0 0 0 0 0 1 1 1 1 IDX1 0 0 0 1 1 0 0 1 1 IDX0 TB12 TB11 TB10 TB9 TB8 TB7 VCO 0 0 GON BT[2] BT[1] BT[0] MG 1 1 0 1 0 1 0 1 0 0 VGL [4] VGL [3] VGL [2] 0 0 0 0 1 0 0 0 0 0 DK [1] VDV [4] 0 DK [0] VDV [3] PON 0 VDV [2] TB6 DC [2] VRH [3] 0 TB5 DC [1] VRH [2] 0 TB4 DC [0] VRH [1] 0 TB3 AP [2] VRH [0] 0 TB2 AP [1] VC [2] 0 TB1 AP [0] VC [1] 0 TB0 0 VC [0] 0 VDV VDV VCM VCM VCM VCM VCM [0] [1] [0] [4] [3] [2] [1] Setting disabled Setting disabled Setting disabled Setting disabled VGL VGL VGH VGH VGH VGH VGH 0 [1] [0] [4] [3] [2] [1] [0] HD66783 / HD667P21 instructions Set data to transfer Set Index R110h Read instructions Write to R111h Index HD66781's registers No (transfer in procession) TE="0" Yes (transfer allowed) Power-supply side index (IDX2-0) TE="1" (start transfer) Specify IDX[2:0] that includes changed instruction bits in accordance to the instruction list of power-supply/gate drivers (HD66783) or power-supply IC(HD667P21). Serial transfer sequence: gate driver/power supply IC interface Rev.0.5, July.31.2003, page 71 of 196 HD66781 Setting examples 1. (1) (2) (3) (4) (5) 2. (1) (2) (3) (4) (5) (6) (7) Set DC1[2:0], VDV[4:0], VCM of HD66783 to 3'h2, 5'h2, 5'h3 respectively. Instruction set: R111h Data write: 16'h0843 (DC1[2:0]=3'h2, VDV[4:0]=5'h2, VCM[4:0]=5'h3) Instruction set: R110h Data read: (make sure TE=0) Data write: 16'h0102 (TE=1, IDX[2:0]=3'h2) Preliminary Set NL of HD66781 and HD66783 to 6'h20 (NL, AP, FLD are the registers that require a setting in both HD66781 and HD66783). Instruction set: R400h Data write: 16'h0020 Instruction set: R111h Data write: 16'h0800 (GS=0, NL[5:0]=6'h20, SCN[5:0]=6'h00) Instruction set: R110h Data read: (make sure TE=0) Data write: 16'h0102 (TE=1, IDX[2:0]=3'h6) Note 1) Make a same setting to the HD66781 and HD66783 at one time. (1) and (2) are the setting for the HD66781. (3)~(7) are the setting for the HD66783. Rev.0.5, July.31.2003, page 72 of 196 HD66781 Common registers for HD66783 and HD667P21 Preliminary BT[2:0]: Change the output scale of step-up circuits. Adjust the step-up scale according to the voltage in use. To set power consumption lower, it is necessary to set the step-up scale smaller. For details, see the datasheets of HD66783 and HD667P21. VCOMG: Make settings for the output level of VcomL. VCOMG = 0 The low-side output of Vcom is fixed to GND and the instruction (VDV) setting becomes invalid. Outputs from VcomL and VCL are halted. For this reason, the VCOMG setting is related to the power-supply startup sequence. Make a VCOMG setting by following the power-supply setting sequence. The low-side output of Vcom becomes VcomL. The output voltage of VcomL is set by instruction (VDV) setting. VCOMG = 1 is valid when PON = 1. VCOMG = 1 VC[2:0]: Adjust the reference voltages of VREG1OUT, VREG2OUT, and Vci1 voltages according to Vci as the reference voltage. For details, see the datasheets of HD66783 and HD667P21. VRH[3:0]: Set the amplifying scale of VREG1OUT with the values set in VC bits (REGP) as an input. For details, see the datasheets of HD66783 and HD667P21. VCM[4:0]: Make a setting for VcomH (the "High" of Vcom). VcomH can be amplified to VREG1OUT x 0.41 ~ 1.00. When VCM = 5'h01, VcomH is not adjusted by the internal volume adjustment but by an external resistor from VcomR. For details on whether to generate the VcomH level with internal electronic volume or an external resistor, see the datasheets of HD66783 and HD667P21. VDV[4:0]: Set the Vcom alternating amplitude. The setting is invalid without Vcom alternating drive. For details, see the datasheets of HD66783 and HD667P21. Registers of HD66783 AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity is enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = "3'h0" to halt the operation of operational amplifiers and step-up circuits to reduce the current consumption. To set AP[2:0] otherwise, it starts step-up circuits to output VGH. For details, see the datasheets of HD66783. DC0[2:0]: Select the operation frequency of step-up circuit 1. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. For details, see the datasheets of HD66783. GON: When GON=0, the output level of G1~G320 pins of HD66783 becomes VGH and the Vcom level becomes GND. Rev.0.5, July.31.2003, page 73 of 196 HD66781 Preliminary PON: Set start/halt of VGL, VCL operations. Set PON according to the power supply start sequence. PON=0: Halt PON=1: Start EQM: Select the operation mode of Vcom2 output. Set EQM = 0. DK: Control the start-up of DDVDH. See "Instruction Setting Flow" (p.185) for details on the setting. VCM[4:0]: Make a setting for VcomH (the High voltage of Vcom). VcomH can be amplified to the level VREG1OUT x 0.40 ~ 0.98. When VCM[4:0] = 5'h0F, internal volume is halted and VcomH is adjusted by an external resistor from VcomR. See the datasheet of HD66783 whether to generate VcomH level with internal electronic volume or an external resistor. DC1[2:0]: Select the operation frequency of step-up circuit 2. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. See the datasheet of HD66783 for details. SCN[5:0]: Set the start position of scanning gate bus line. For details, see the datasheets of HD66783. NL[5:0]: Set the number of liquid crystal drive raster-rows. The number of raster-rows can be set to 8 multiples. The value should be set equal to or more than to drive the number of raster-rows required for the panel size. Note: Set SCN[5:0] and NL[5:0] to satisfy the following equation: (Output start position) + (Number of drive raster-rows) - 1 320 (raster-rows) GS: Set the scan direction of gate bus lines. The direction is changeable according to the gate driver's position on the assembly. For details, see the datasheets of HD66783. FLD[1:0]: Set the number of valid lines to drive n-line interlacing. For details, see the datasheets of HD66783. Registers of HD667P21 AP[2:0]: Adjust the amount of constant current in the operational amplifier in the liquid crystal drive power supply. When the amount of constant current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. When no display operation is required, set AP[2:0] = "3'h0" to halt the operation of operational amplifier and step-up circuits to reduce the current consumption. If AP[2:0] is set otherwise, it starts step-up circuit to output VLOUT1, VLOUT2. For details, see the datasheets of HD667P21. DC[2:0]: Select the operation frequency of step-up circuit 1. If the step-up operation frequency is set high, display quality will be enhanced due to increased drive capacity of step-up circuit, while power consumption will be increased. Make an adjustment taking both display quality and power consumption into consideration. For details, see the datasheets of HD66783. GON: When GON=0, the Vcom level becomes GND. Rev.0.5, July.31.2003, page 74 of 196 HD66781 Preliminary PON: Set start/halt of VLOUT3 operation. Set PON according to the power supply start sequence. PON=0: Halt PON=1: Start VCM[4:0]: Make a setting for VcomH (the High voltage of Vcom). VcomH can be amplified to the level VREG1OUT x 0.41 ~ 1.00. When VCM[4:0] = 5'h1F, internal volume is halted and VcomH is adjusted by an external resistor from VcomR. See the datasheet of HD667P21 whether to generate VcomH level with internal electronic volume or an external resistor. VGH[4:0]: Set the VGH regulator output level. The setting can be made from 2.82 to 4.06 times of REGP voltage. VGL[4:0]: Set the VGL regulator output level. The setting can be made from -1.60 to -2.84 times of REGP voltage. Rev.0.5, July.31.2003, page 75 of 196 HD66781 RAM Address set in horizontal/vertical directions (R200h/R201h) R/W W W RS 1 1 IB15 0 0 IB14 0 0 IB13 0 0 IB12 0 0 IB11 0 0 IB10 0 0 IB9 0 0 IB8 0 AD [16] IB7 AD [7] AD [15] IB6 AD [6] AD [14] IB5 AD [5] AD [13] IB4 AD [4] AD [12] Preliminary IB3 AD [3] AD [11] IB2 AD [2] AD [10] IB1 AD [1] AD [9] IB0 AD [0] AD [8] Note : Top R200h, Bottom R201h AD[16:0]: Initialize GRAM address at AC (Address Counter). The address counter is automatically updated in accordance with AM, I/D settings after data are written to GRAM. Data can be written consecutively without making a new address setting. The address counter is not automatically updated when data are read out from GRAM. Table 45 AD[16:0] 17'h00000 - 17'h000EF 17'h00100 - 17'h001EF 17'h00200 - 17'h002EF 17'h00300 - 17'h003EF 17'h00400 - 17'h004EF : 17'h13F00 - 17'h13CEF 17'h13F00 - 17'h13DEF 17'h13F00 - 17'h13EEF 17'h13F00 - 17'h13FEF GRAM address range GRAM Setting Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 Bitmap data for G5 : Bitmap data for G317 Bitmap data for G318 Bitmap data for G319 Bitmap data for G320 Note 1) An address set is made every frame within the GRAM address range set by AD[16:0] at the falling edge of VSYNC when RGB interface (RM=1) is selected. Note 2) An address set is made when instructions are executed in the internal clock operation or the VSYNC interface mode (RM = 0). Note 3) Register values are loaded in both horizontal/vertical address counters when a setting is made for either one of the R200h/R201h registers. Rev.0.5, July.31.2003, page 76 of 196 HD66781 Write Data to GRAM (R202h) R/W W RS 1 Preliminary The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface. The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface . RGB interface WD[17:0]: All data are expanded into 18 bits internally before being written to GRAM. The way of expanding data into 18 bits is different according to the interface. The grayscale level is selected according to the GRAM data. The address is automatically updated according to the setting with the AM and I/D bits after data are written to GRAM. During the standby mode, no access is allowed to GRAM. When the 8 or 16 bit interface modes are selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively to expand the 8/16- bit data into the 18-bit data internally. During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid conflicts between writing through the RGB interface and writing through system interface. When the 18-bit RGB interface is selected, the18-bit data in PD17-0 bits are written, and 262,144 colors are available. When the 16-bit RGB interface is selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively, and 65,536 colors are available. The upper 3 bits of OSD image data are used as a transmission-rate bit ( channel). Table 46 OSD ODF 0 1 1 * 0 1 BGR = 0 D17 R5 R5 2 D16 R4 R4 1 D15 R3 R3 0 D14 R2 R2 R4 D13 R1 R1 R3 D12 R0 2 R2 D11 G5 G5 R1 D10 G4 G4 R0 D9 G3 G3 G4 D8 G2 G2 G3 D7 G1 G1 G2 D6 G0 1 G1 D5 B5 B5 G0 D4 B4 B4 B4 D3 B3 B3 B3 D2 B2 B2 B2 D1 B1 B1 B1 D0 B0 0 B0 Table 47 OSD ODF 0 1 1 * 0 1 BGR =1 D17 B5 B5 0 D16 B4 B4 1 D15 B3 B3 2 D14 B2 B2 B4 D13 B1 B1 B3 D12 B0 0 B2 D11 G5 G5 B1 D10 G4 G4 B0 D9 G3 G3 G4 D8 G2 G2 G3 D7 G1 G1 G2 D6 G0 1 G1 D5 R5 R5 G0 D4 R4 R4 R4 D3 R3 R3 R3 D2 R2 R2 R2 D1 R1 R1 R1 D0 R0 2 R0 Rev.0.5, July.31.2003, page 77 of 196 HD66781 Table 48 2 1 Preliminary channel 0 transmission rate displayed picture 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0% 25% 75% 50% 100% Base image display Setting disabled Base image 75%+OSD 25% Base image 25%+OSD 75% Base image 50%+OSD 50% Setting disabled OSD image display Setting disabled 18-bit interface (Base image:262,144 colors, OSD image: 32,768 colors) DB input pins 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G4 G2 G2 G3 G1 G1 G2 G0 1 G1 B5 B5 G0 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 RAM data write in 18-bit interface (Base image 262,144 colors/OSD image 8,192 colors) Rev.0.5, July.31.2003, page 78 of 196 HD66781 Preliminary 16-bit interface 1 transmission TRI = 0, DFM = * (Base image: 65, 536 colors/OSD image: 8,192 colors) Base image data format Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image data format 1 (ODF = 0) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment R5 R4 R3 R2 R5 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B5 0 OSD image data format 1 (ODF = 1) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment 2 1 0 R5 R4 R3 R2 R5 G5 G4 G3 G2 G1 B5 B4 B3 B2 B5 RAM data write in 16-bit interface (Base image 65,536 colors/OSD image 32,768 colors) Rev.0.5, July.31.2003, page 79 of 196 HD66781 Preliminary 16-bit interface 2 transmissions TRI = 1, DFM = 0 (Base image:262,144 colors, OSD image: 32,768 colors) 1st transmission DB DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 2nd transmission DB 17 DB 16 input pins 17 GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G4 G2 G2 G3 G1 G1 G2 G0 1 G1 B5 B5 G0 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 16-bit interface 2 transmissions TRI = 1, DFM = 1 (Base image:262,144 colors, OSD image: 32,768 colors) 1st transmission 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 input pins DB 2 DB 1 GRAM write data WD [17 ] WD [16 ] WD [15 ] WD [14 ] WD [13 ] WD [12 ] WD [11 ] WD [10 ] WD [9 ] WD [8 ] WD [7 ] WD [6 ] WD [5 ] WD [4 ] WD [3 ] WD [2 ] WD [1 ] WD [0 ] RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G4 G2 G2 G3 G1 G1 G2 G0 1 G1 B5 B5 G0 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 RAM data write in 16-bit interface (Base image 262,144 colors/OSD image 32,768 colors) 9-bit interface (Base image 262,144 colors/OSD image 32,786 colors) 1st transmission (Upper) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 2nd transmission (Lower) DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB picture Assignment OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 RAM data write in 9-bit interface (Base image 262,144 colors /OSD image 32,768 colors) Rev.0.5, July.31.2003, page 80 of 196 HD66781 8-bit interface, 2 transmissions TRI = 0, DFM = * (Big endian) (Base image 65,536 colors/ OSD 8,192 colors) Base image data format 1st transmission (Upper) Input pin 2nd transmission (Lower) Preliminary DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB pixel Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image data format (ODF = 0) 1st transmission (Upper) Input pin 2nd transmission (Lower) DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] OSD data ODF = 0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD image data format (ODF = 1) 1st transmission (Upper) Input pin 2nd transmission (Lower) DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] OSD data ODF = 0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 RAM data write in 8-bit interface, big endian (Base image/OSD image) Rev.0.5, July.31.2003, page 81 of 196 HD66781 8-bit interface, 3 transmissions TRI = 1, DFM = 0 (Base image 262,144 colors/ OSD 32,768 colors) 1st transmission Preliminary 2nd transmission DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 3rd transmission DB 13 DB 12 DB 11 DB 10 Input pin DB 11 DB 10 GRAM Write data RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 8-bit interface, 3 transmissions TRI = 1, DFM = 1 (Base image 262,144 colors/ OSD 32,768 colors) 1st transmission Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 2nd transmission DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd transmission DB 15 DB 14 DB 13 DB 12 GRAM Write data RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 RAM data write in 8-bit interface, 3 transmissions (Base image/OSD image) Rev.0.5, July.31.2003, page 82 of 196 HD66781 Preliminary 8-bit interface, 2 transmissions TRI = 0, DFM = * (Little endian) (Base image 65,536 colors/ OSD 8,192 colors) Base image data format 2nd transmission (Upper) 1st transmission (Lower) DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 Input pin GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB pixel Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image data format (ODF = 0) 2nd transmission (Upper) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 1st transmission (Lower) DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] OSD data ODF = 0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD image data format (ODF = 1) 2nd transmission (Upper) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 1st transmission (Lower) DB 14 DB 13 DB 12 DB 11 DB 10 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] OSD data ODF = 0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 RAM data write in 8-bit interface, little endian (Base image/OSD image) Rev.0.5, July.31.2003, page 83 of 196 HD66781 RGB 18-bit interface (Base image 262,144 colors, OSD image 32,768 colors) Input pin PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 Preliminary PD 2 PD 1 PD 0 GRAM Write data RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 Note : RAM write through RGB interface requires index register settings. RGB 18-bit interface (Base/OSD image display) RGB 16-bit interface (Base image: 65, 536 colors/OSD image: 8,192 colors) Base image data format Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] RGB picture Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 OSD image data format 1 (ODF = 0) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] OSD data ODF = 0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 OSD image data format 1 (ODF = 1) Input pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] OSD data ODF = 0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 RGB 16-bit interface (Base/OSD image display) Rev.0.5, July.31.2003, page 84 of 196 HD66781 RGB 6-bit interface, 3 transmissions (Base image 266,144 colors/ OSD 32,768 colors) 1st transmission Input pin Preliminary 2nd transmission DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 3rd transmission DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 GRAM Write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB pixel assignment OSD data ODF = 0 OSD data ODF = 1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 RGB 6-bit interface (Base/OSD image) Table 49 GRAM data and LCD output level (REV = 0) Selected grayscale level Positive Negative V0 V63 V1 V62 V2 V61 V3 V60 V4 V59 V5 V58 V6 V57 V7 V56 V8 V55 V9 V54 V10 V53 V11 V52 V12 V51 V13 V50 V14 V49 V15 V48 V16 V47 V17 V46 V18 V45 V19 V44 V20 V43 V21 V42 V22 V41 V23 V40 V24 V39 V25 V38 V26 V37 V27 V36 V28 V35 V29 V34 V30 V33 V31 V32 GRAM data RGB 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F Selected grayscale level Positive Negative V32 V31 V33 V30 V34 V29 V35 V28 V36 V27 V37 V26 V38 V25 V39 V24 V40 V23 V41 V22 V42 V21 V43 V20 V44 V19 V45 V18 V46 V17 V47 V16 V48 V15 V49 V14 V50 V13 V51 V12 V52 V11 V53 V10 V54 V9 V55 V8 V56 V7 V57 V6 V58 V5 V59 V4 V60 V3 V61 V2 V62 V1 V63 V0 GRAM data RGB 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F Rev.0.5, July.31.2003, page 85 of 196 HD66781 RAM Access through RGB-I/F and System I/F Preliminary The HD66781 writes all display data to the internal RAM even in the RGB-I/F mode. Through the RGBI/F mode, only the data for the moving picture area as well as for the frames to update screens can be transmitted. By writing data in the high-speed write mode (HWM = 1) and with the window address function, the HD66781 achieves high-speed access to RAM with low power consumption while displaying moving pictures. In the frames other than the moving picture screen update, the display data in the area other than the moving picture area can be updated through a system interface. RAM access is also possible through the system interface even in the RGB-I/F mode. In the RGB interface mode, data are written to RAM in synchronization with the DOTCLK input during ENABLE = "Low". When writing data in the RGB-I/F mode through the system interface, it is necessary to set ENABLE "High" to stop writing through the RGB interface. After accessing RAM through the system interface, wait an enough time for the write/read bus cycle before starting RAM access through the RGB interface. Screen update Screen update In dex R22 Index R202 Updating moving pict ur e area Address Set Data update in the area other than moving picture area Not e 1) Updat ing still pictur e area Address Set RM= 1 Index R202 Updating moving pict ur e area Not e 1) An address set is made every falling edge of VSYNC in the RGB interface mode. N ot e 2) An address set and an index set (R202h) must be made before RAM access through the RGB interface. N ot e 3) Write data in the high-speed write mode (HWM = 1) in the RGB interface mode. 6/2 00:00 6/25 00:00 6/2 00:00 6/25 00:00 Moving picture area Moving picture area Updating still picture area while displaying a moving picture Rev.0.5, July.31.2003, page 86 of 196 HD66781 Read Data from GRAM (R202h) R/W R RS 1 Preliminary RAM read data (RD[17:0]) are assigned differently to the DB[17:0] pins according to an interface . RD[17:0]: Read 18-bit data from GRAM. The RAM read data (RD[17:0]) are assigned differently to the DB[17:0] pins according to an interface. When data are read out from GRAM to the microcomputer, the first-word data read immediately after the GRAM address set are latched in the internal read-data latch, and the data in the data bus (DB17-0) are nullified. The data are read as valid data from the second word. When the 8-/16-bit interfaces are selected, the GRAM data in the LSBs of R and B pixels are not read out. When reading out OSD data, it takes the data format when ODF = 0. This function is not available in the RGB interface mode. Set TRI = 0 while data read is executed. 18-bit interface GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 16-bit interface GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Read data from GRAM: 18/16-bit interface Rev.0.5, July.31.2003, page 87 of 196 HD66781 9-bit interface (2 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 Preliminary B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB 17 DB 16 DB 15 DB DB DB 14 13 12 First transmission DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB DB DB DB 14 13 12 11 Second transmission DB 10 DB 9 8-bit interface (2 transmissions(Big endian)/3 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB 17 DB 16 DB 15 DB DB DB 14 13 12 First transmission DB 11 DB 10 DB 17 DB 16 DB 15 DB DB DB 14 13 12 second transmission DB 11 DB 10 8-bit interface (2 transmissions(Little endian)/3 transmissions) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] output pin DB 17 DB 16 DB 15 DB DB DB 14 13 12 second transmission DB 11 DB 10 DB 17 DB 16 DB 15 DB DB DB 14 13 12 First transmission DB 11 DB 10 Read data from GRAM: 9/8-bit interface I/D,AM bit Setting HSA,HEA VSA,VEA Address set : N set First word Dummy read (void data) GRAM - read data latch Read (data at address N) read data latch - DB17-0 Address set : Mset First word Dummy read (void data) GRAM - read data latch Read (data at address N) read data latch - DB17-0 Read out data to microcomputer Second word Second word GRAM read sequence Rev.0.5, July.31.2003, page 88 of 196 HD66781 RAM Write Data Mask 1/2 (R203h/R204h) R/W W W RS 1 1 IB15 0 0 IB14 0 0 IB13 WM [11] 0 IB12 WM [10] 0 IB11 WM [9] 0 IB10 WM [8] 0 IB9 WM [7] 0 IB8 WM [6] 0 IB7 0 0 IB6 0 0 IB5 WM [5] WM [17] IB4 WM [4] WM [16] Preliminary IB3 WM [3] WM [15] IB2 WM [2] WM [14] IB1 WM [1] WM [13] IB0 WM [0] WM [12] Note 1) Top R203, bottom R204 WM[17:0]: Write-mask data by bit when the data are written to GRAM. For example, if WM17 = 1, the WM17 write-mask the MSB of the data to write to GRAM so that the data in the MSB is not written to GRAM. The rest of WM16 ~ 0 bits also write-mask the data in the corresponding bits of GRAM write data as well when they are set to 1. The WM17-0 bits write-mask the 18-bit data to write to GRAM. Note 1) This function is not available in the RGB-I/F mode. Note 2) OSD image data are written to RAM in the ODF = 0 format. The write-mask setting for OSD images must be made for the ODF = 0 format. Write mask WM [17] WM [16] WM [15] WM [14] WM [13] WM [12] WM [11] WM [10] WM [9] WM [8] WM [7] WM [6] WM [5] WM [4] WM [3] WM [2] WM [1] WM [0] GRAM Write data OSD data R5 R5 R4 R4 R3 R3 R2 R2 R1 R1 R0 2 G5 G5 G4 G4 G3 G3 G2 G2 G1 G1 G0 1 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 0 RAM write data mask Rev.0.5, July.31.2003, page 89 of 196 HD66781 Window Address Control Instructions Window horizontal RAM address Start/End (R210h/ R211h) Window vertical RAM address Start/End (R212h/R213h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB7 HSA 0 [7] HEA 0 [7] VSA VSA [8] [7] VEA VEA [8] [7] IB8 IB6 HSA [6] HEA [6] VSA [6] VEA [6] IB5 HSA [5] HEA [5] VSA [5] VEA [5] IB4 HSA [4] HEA [4] VSA [4] VEA [4] IB3 HSA [3] HEA [3] VSA [3] VEA [3] IB2 HSA [2] HEA [2] VSA [2] VEA [2] Preliminary R50 R51 R52 R53 W W W W 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB1 HSA [1] HEA [1] VSA [1] VEA [1] IB0 HSA [0] HEA [0] VSA [0] VEA [0] HSA[7:0] Specify the start position of a window-address range in the horizontal direction by address. HEA[7:0] Specify the end position of a window-address range in the horizontal direction by address. Data are written to a rectangular area within GRAM from the address specified by HSA to the address specified by HEA. The setting of the address is required before writing data to RAM. Make sure the address is set to satisfy 8'h00 HSA< HEA 8'hEF and 8'h4 HEA - HSA. VSA[7:0] Specify the start position of a window-address range in the vertical direction to access to RAM. VEA[7:0] Specify the end position of a window-address range in the vertical direction to access to RAM. Data are written to a rectangular area within GRAM from the address specified by VSA to the address specified by VEA. The setting of addresses is required before writing data to RAM. Make sure the addresses are set to satisfy 9'h000 VSA< VEA 9'h19F. 17'h000-00 HSA VSA H EA Window Address area Window-address range 8'h00 HSA< HEA 8'hEF, 8'h04 HEA - HSA, 9'h00 VSA < VEA 9'h19F 17'h19F-EF VE A GRAM address map and window-address range Note 1) Set a window-address range within the GRAM address map. Note 2) In the high-speed write mode, data are written to GRAM by one horizontal line. Write data to GRAM by horizontal line unit. Note 3) Make an address set within the window address area. In the high-speed write mode, make an address set from the first line of the window address area. Rev.0.5, July.31.2003, page 90 of 196 HD66781 Control (R300h ~ R309h) R /W R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 Preliminary IB2 IB1 IB0 W W W W W W W W W W 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PK PK PK P1[2] P1[1] P1[0] PK PK PK 0 0 P3[2] P3[1] P3[0] PK PK PK 0 0 P5[2] P5[1] P5[0] PR PR PR 0 0 P1[2] P1[1] P1[0] VR VR VR VR VR P1[4] P1[3] P1[2] P1[1] P1[0] PK PK PK 0 0 N1[2] N1[1] N1[0] PK PK PK 0 0 N3[2] N3[1] N3[0] PK PK PK 0 0 N5[2] N5[1] N5[0] PR 0 0 N1[2] PR PR N1[1] N1[0] VR VR VR VR VR N1[4] N1[3] N1[2] N1[1] N1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PK PK PK 0 P0[2] P0[1] P0[0] PK PK PK 0 P2[2] P2[1] P2[0] PK PK PK 0 P4[2] P4[1] P4[0] PR PR PR 0 P0[2] P0[1] P0[0] VR VR VR VR P0[3] P0[2] P0[1] P0[0] PK PK PK 0 P0[2] P0[1] P0[0] PK PK PK 0 N2[2] N2[1] N2[0] PK PK PK 0 N4[2] N4[1] N4[0] PR PR PR 0 N0[2] N0[1] N0[0] VR VR VR VR N0[3] N0[2] N0[1] N0[0] PKP5-0[2:0]: PRP1-0[2:0]: VRP(N)0[3:0]: PKN5-0[2:0]: PRN1-0[2:0]: VRP(N)1[4:0]: fine adjustment registers for positive polarity gradient adjustment registers for positive polarity amplitude adjustment resistor for positive polarity fine adjustment registers for negative polarity gradient adjustment registers for negative polarity amplitude average adjustment resistor for negative polarity Rev.0.5, July.31.2003, page 91 of 196 HD66781 Base image display control instructions Number of Line (R400h) Base image display position (R401h) Base picture RAM Address (R402h) Base picture RAM Address (R403h) Vertical scroll Control (R404h) Base image expansion area/start line address (R405h) Base image expansion area/end line address (R406h) R /W R400 R401 R402 Preliminary RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W W W W W W W 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSA [8] BEA [8] VL [8] ESA [8] EEA [8] 0 0 BSA [7] BEA [7] VL [7] ESA [7] EEA [7] 0 0 BSA [6] BEA [6] VL [6] ESA [6] EEA [6] NL1 NL1 NL1 NL1 NL1 NL1 [5] [4] [3] [2] [1] [0] 0 BSA [5] BEA [5] VL [5] ESA [5] EEA [5] 0 BSA [4] BEA [4] VL [4] ESA [4] EEA [4] 0 BSA [3] BEA [3] VL [3] ESA [3] EEA [3] 0 BSA [2] BEA [2] VL [2] ESA [2] EEA [2] VLE REV BSA [1] BEA [1] VL [1] ESA [1] EEA [1] BSA [0] BEA [0] VL [0] ESA [0] EEA [0] R403 R404 R405 R406 Base image control instructions NL0[5:0]: Set the number of liquid crystal drive raster-rows. The number of raster-rows can be set to 8 multiples. The GRAM address mapping is made irrespective of the value set for the number of raster-rows to drive liquid crystal. The value should be set equal to or more than to drive the number of raster-rows required for the panel size. REV: When REV = 1, a reverse display is shown within the display area. The grayscale level inversion enables to use same data to display on both normally white and normally black panels. The REV setting is effective for both OSD and base image areas. The source outputs during front and back porches and a blank period during partial display mode depend on the setting of PTS bits. Table 50 Source output level in display area Positive polarity Negative polarity 18'h00000 V63 V0 0 : : : 18'h3FFFF V0 V63 18'h00000 V0 V63 1 : : : 18'h3FFFF V63 V0 Note 1) The source outputs during front and back porches and a blank period during partial display mode depend on the setting of PTS bits. REV0 GRAM data Rev.0.5, July.31.2003, page 92 of 196 HD66781 Preliminary VLE: When VLE = 1, settings for the vertical scroll display is made valid. The start line is displayed according to the VL[8:0] setting. The raster-rows that display a base image are scrolled by the number of lines set by VL bits. OSD area is not affected by the base-picture scrolling. This function is not available while external display interface is selected. While external display interface is selected, make sure that VLE= 0. Table 51 VLE 0 1 Base image Fixed display Scrolling display Note 1) Scroll function is not available during the interlaced drive (FLD = 2'h3) BSA[8:0]/BEA[8:0]: Set the start line address (BSA) and the end line address (BEA) of the base image display RAM area. Display RAM data from the one set at BSA bits from the first line. Make sure that base image display RAM area (BSA/BEA) is equal to or more than the number of raster-rows driving a panel (= NL BSA - BEA). In case of BSA - BEA NL, outside the base image area becomes non-lit display. VL[8:0] Set the number of raster-rows that are scrolled for a base image. The numbers of raster-rows set by VL bits are scrolled within the base image. ESA[8:0]/EEA[8:0] Set the start line address (ESA) and the end line address (EEA) of the area which is magnified in the base image display RAM area. A base image in the area specified with ESA and EEA is magnified on display. Make sure that BSA ESA EEA BEA. A magnified base image is not available with the scrolling function. Table 52 Liquid crystal drive raster-rows Number of raster-rows Setting disabled 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 NL[5:0] 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 NL[5:0] 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 Number of raster-rows 168 176 184 192 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 Rev.0.5, July.31.2003, page 93 of 196 HD66781 OSD control instructions OSD image 1 display position (R500h) OSD image 1 RAM Address /Start line Address (R501h) OSD image 1 RAM Address /End line Address (R502h) OSD image 2 display position (R503h) OSD image 2 RAM Address/Start line Address (R504h) OSD image 2 RAM Address/End line Address (R505h) OSD image 3 display position (R506h) OSD image 3 RAM Address/Start line Address (R507h) OSD image 3 RAM Address/End line Address (R508h) R /W R500 R501 R502 RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 Preliminary IB2 IB1 IB0 W W W 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODP 0 [8] OSA 0 [8] OEA 0 [8] ODP 1 [8] OSA 1 [8] OEA 1 [8] ODP 2 [8] OSA 2 [8] OEA 2 [8] ODP 0 [7] OSA 0 [7] OEA 0 [7] ODP 1 [7] OSA 1 [7] OEA 1 [7] ODP 2 [7] OSA 2 [7] OEA 2 [7] ODP 0 [6] OSA 0 [6] OEA 0 [6] ODP 1 [6] OSA 1 [6] OEA 1 [6] ODP 2 [6] OSA 2 [6] OEA 2 [6] ODP 0 [5] OSA 0 [5] OEA 0 [5] ODP 1 [5] OSA 1 [5] OEA 1 [5] ODP 2 [5] OSA 2 [5] OEA 2 [5] ODP 0 [4] OSA 0 [4] OEA 0 [4] ODP 1 [4] OSA 1 [4] OEA 1 [4] ODP 2 [4] OSA 2 [4] OEA 2 [4] ODP 0 [3] OSA 0 [3] OEA 0 [3] ODP 1 [3] OSA 1 [3] OEA 1 [3] ODP 2 [3] OSA 2 [3] OEA 2 [3] ODP 0 [2] OSA 0 [2] OEA 0 [2] ODP 1 [2] OSA 1 [2] OEA 1 [2] ODP 2 [2] OSA 2 [2] OEA 2 [2] ODP 0 [1] OSA 0 [1] OEA 0 [1] ODP 1 [1] OSA 1 [1] OEA 1 [1] ODP 2 [1] OSA 2 [1] OEA 2 [1] ODP 0 [0] OSA 0 [0] OEA 0 [0] ODP 1 [0] OSA 1 [0] OEA 1 [0] ODP 2 [0] OSA 2 [0] OEA 2 [0] R503 R504 R505 W W W 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R506 R507 R508 W W W 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODP0[8:0]: ODP0 : Set the display position of OSD image 1. ODP1[8:0]: ODP1 : Set the display position of OSD image 2. ODP2[8:0]: ODP2 : Set the display position of OSD image 3. The display areas for OSD images 1, 2, 3 should not overlap one another. Set each area as follows. Display area of OSD image 1: ODP0, ODP0+(OEA0 - OSA0) Display area of OSD image 2: ODP1, ODP1+(OEA1 - OSA1) Display area of OSD image 3: ODP2, ODP2+(OEA2 - OSA2) Make sure that display area of OSD image 1 < Display area of OSD image 2 < Display area of OSD image 3. If ODP0 is set "9'h000", OSD image 1 is displayed from the start line of the base image on the first panel. The OSD is not available during interlaced drive (FLD = 2'h3). OSA0[8:0] OEA0[8:0]: OSA0, OEA0 : Set the start line address and end line address for display RAM area of the OSD image 1. Rev.0.5, July.31.2003, page 94 of 196 HD66781 Preliminary OSA1[8:0] OEA1[8:0]: OSA1, OEA1 : Set the start line address and end line address for display RAM area of the OSD image 2. OSA2[8:0] OEA2[8:0]: OSA2, OEA2 : Set the start line address and end line address for display RAM area of the OSD image 3. Rev.0.5, July.31.2003, page 95 of 196 HD66781 Preliminary Instruction list Main Category Upper bits of Index Index Status Read Display Control System Sub Category Index Command Index Status Read Start Oscillation Device Code Read Driver Output Control Liquid Crystal Drive Alternating Control Entry Mode Resizing Control (1) Resizing Control (2) Setting Disabled Display Control (1) Display Control (2) Display Control (3) Setting Disabled Display Control (4) External Display Interface Control (1) Upper Code IB15 * 0 * 0 0 0 TRI (0) 0 RSEV[7] (0) 0 0 0 IB14 * 0 * 0 0 0 DFM (0) 0 RSEV[6] (0) OSDE[2] (0) 0 0 FRCON (0) 0 0 0 0 0 0 0 0 IB13 * 0 * 0 0 0 0 0 RSEV[5] (0) OSDE[1] (0) 0 0 D16B (0) 0 0 0 0 0 0 0 0 IB12 * 0 * 0 LTPS (0) 0 BGR (0) 0 RSEV[4] (0) OSDE[0] (0) 0 0 IB11 * 0 * 0 0 FLD[1] (0) 0 0 RSEV[3] (0) 0 FP[3] (1) 0 IB10 ID10 0 * 1 0 FLD[0] (1) 0 0 RSEV[2] (0) 0 FP[2] (0) PTS[2] (0) 0 0 0 0 0 FWI[2] (0) SWI[2] (0) 0 DPWI[2] (0) 0 FWE[2] (0) SWE[2] (0) 0 DPWE[2] (0) EQWE[2] (0) SAP[2] (0) 0 TB[10] (0) 0 0 IB9 ID9 0 * 1 0 B/C (0) HWM (0) RCV[1] (0) RSEV[1] (0) 0 FP[1] (0) PTS[1] (0) 0 0 DIVI[1] (0) DIVE[1] (1) 0 FWI[1] (0) SWI[1] (0) 0 DPWI[1] (0) EQWI[1] (0) FWE[1] (0) SWE[1] (0) 0 DPWE[1] (0) EQWE[1] (0) SAP[1] (0) 0 TB[9] (0) 0 0 IB8 ID8 L8 * 1 SS (0) EOR (0) 0 RCV[0] (0) RSEV[0] (0) BASEE (0) FP[0] (0) PTS[0] (0) 0 RM (0) DIVI[0] (0) DIVE[0] (0) 0 FWI[0] (0) SWI[0] (0) 0 DPWI[0] (0) EQWI[0] (0) FWE[0] (0) SWE[0] (0) 0 DPWE[0] (0) EQWE[0] (0) SAP[0] (0) TE (0) TB[8] (0) 0 AD[16] (0) WM[6] (0) 0 IB7 ID7 L7 * 1 0 0 0 0 0 IB6 ID6 L6 * 0 0 0 0 0 0 IB5 ID5 L5 * 0 0 NW[5] (0) ID[1] (1) RCH[1] (0) 0 Lower Code IB4 ID4 L4 * 0 0 NW[4] (0) ID[0] (1) RCH[0] (0) 0 DTE (0) 0 PTG[0] (0) 0 DM[0] (0) RTNI[4] (1) RTNE[4] (1) VSPL (0) 0 0 0 0 IB3 ID3 L3 * 0 0 NW[3] (0) AM (0) 0 0 IB2 ID2 L2 * 0 0 NW[2] (0) 0 0 0 IB1 ID21 L1 * 0 0 NW[1] (0) OSD (0) RSR[1] (0) 0 D[1] (0) BP[1] (0) ISC[1] (0) COL[1] (0) RIM[1] (0) RTNI[1] (0) RTNE[1] (1) EPL (0) FTI[1] (0) STI[1] (0) SDTI[1] (0) DPTI[1] (0) 0 FTE[1] (0) STE[1] (0) SDTE[1] (0) DPTE[1] (0) 0 SLP (0) IDX[1] (0) TB[1] (0) AD[1] (0) AD[9] (0) WM[1] (0) WM[13] (0) HSA[1] (0) HEA[1] (1) VSA[1] (0) VEA[1] (1) PKP0[1] (0) PKP2[1] (0) PKP4[1] (0) PRP0[1] (0) VRP0[1] (0) PKN0[1] (0) PKN2[1] (0) PKN4[1] (0) PRN0[1] (0) VRN0[1] (0) NL[1] (1) VLE (0) BSA[1] (0) BEA[ ] (1) VL[1] (0) ESA[ ] (0) EEA[ ] (0) ODP0[1] (0) OSA0[1] (0) OEA0[1] (0) ODP1[1] (0) OSA1[1] (0) OEA1[1] (0) ODP2[1] (0) OSA2[1] (0) OEA2[1] (0) IB0 ID0 L0 1 1 0 NW[0] (0) ODF (0) RSR[0] (0) RSEH (0) D[0] (0) BP[0] (0) ISC[0] (0) COL[0] (0) RIM[0] (0) RTNI[0] (0) RTNE[0] (0) DPL (0) FTI[0] (0) STI[0] (0) SDTI[0] (0) DPTI[0] (0) 0 FTE[0] (0) STE[0] (0) SDTE[0] (0) DPTE[0] (0) 0 STB (0) IDX[0] (0) TB[0] (0) AD[0] (0) AD[8] (0) WM[0] (0) WM[12] (0) HSA[0] (0) HEA[0] (1) VSA[0] (0) VEA[0] (1) PKP0[0] (0) PKP2[0] (0) PKP4[0] (0) PRP0[0] (0) VRP0[0] (0) PKN0[0] (0) PKN2[0] (0) PKN4[0] (0) PRN0[0] (0) VRN0[0] (0) NL[0] (1) REV (0) BSA[0] (0) BEA[0] (1) VL[0] (0) ESA[0] (0) EEA[0] (0) ODP0[0] (0) OSA0[0] (0) OEA0[0] (0) ODP1[0] (0) OSA1[0] (0) OEA1[0] (0) ODP2[0] (0) OSA2[0] (0) OEA2[0] (0) Note SR 0** 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch-0FFh 0 0 0 0 0 0 0 0 PTG[1] (0) 0 DM[1] (0) 0 RTNE[5] (0) 0 0 0 0 0 0 BP[3] (1) ISC[3] (0) 0 0 RTNI[3] (0) RTNE[3] (1) HSPL (0) 0 0 0 0 0 BP[2] (0) ISC[2] (0) 0 0 RTNI[2] (0) RTNE[2] (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWI[4] (0) SWI[4] (0) 0 DPWI[4] (0) 0 FWE[4] (0) SWE[4] (0) 0 DPWE[4] (0) 0 0 0 0 0 0 FWI[3] (0) SWI[3] (0) 0 DPWI[3] (0) 0 FWE[3] (0) SWE[3] (0) 0 DPWE[3] (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 RTNE[6] (0) 0 0 0 0 0 Frame Cycle Adjustment Contro External Display Interface Control (2) External Display Interface Control (3) Gate Driver/LTPS Liquid Crystal Panel Interface Control (1) Gate Driver/LTPS Liquid Crystal Panel Interface Control (2) Gate Driver/LTPS Liquid Crystal Panel Interface Control (3) Gate Driver/LTPS Liquid Crystal Panel Interface Control (4) Setting Disabled Gate Driver/LTPS Liquid Crystal Panel Interface Control (5) Gate Driver/LTPS Liquid Crystal Panel Interface Control (6) Gate Driver/LTPS Liquid Crystal Panel Interface Control (7) Gate Driver/LTPS Liquid Crystal Panel Interface Control (8) Gate Driver/LTPS Liquid Crystal Panel Interface Control (9) Setting Disabled Gate Driver/LTPS Liquid Crystal Panel Interface Control (10) 0 0 0 0 0 0 0 0 0 0 0 FWE[5] (0) SWE[5] (0) 0 DPWE[5] (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTE[2] (0) STE[2] (0) SDTE[2] (0) DPTE[2] (0) 0 DSTB (0) IDX[2] (0) TB[2] (0) AD[2] (0) AD[10] (0) WM[2] (0) WM[14] (0) HSA[2] (0) HEA[2] (1) VSA[2] (0) VEA[2] (1) PKP0[2] (0) PKP2[2] (0) PKP4[2] (0) PRP0[2] (0) VRP0[2] (0) PKN0[2] (0) PKN2[2] (0) PKN4[2] (0) PRN0[2] (0) VRN0[2] (0) NL[2] (1) 0 BSA[2] (0) BEA[2] (1) VL[2] (0) ESA[2] (0) EEA[2] (0) ODP0[2] (0) OSA0[2] (0) OEA0[2] (0) ODP1[2] (0) OSA1[2] (0) OEA1[2] (0) ODP2[2] (0) OSA2[2] (0) OEA2[2] (0) 0 DC[4] (0) 0 0 0 DC[3] (0) 0 0 0 0 AP[2] (0) 0 TB[6] (0) AD[6] (0) AD[14] (0) 0 AP[1] (0) 0 TB[5] (0) AD[5] (0) AD[13] (0) WM[5] (0) WM[17] (0) HSA[5] (0) HEA[5] (1) VSA[5] (0) VEA[5] (1) 0 0 0 0 0 0 0 0 0 0 NL[5] (1) 0 BSA[5] (0) BEA[5] (1) VL[5] (0) ESA[5] (0) EEA[5] (0) ODP0[5] (0) OSA0[5] (0) OEA0[5] (0) ODP1[5] (0) OSA1[5] (0) OEA1[5] (0) ODP2[5] (0) OSA2[5] (0) OEA2[5] (0) 0 AP[0] (0) 0 TB[4] (0) AD[4] (0) AD[12] (0) WM[4] (0) WM[16] (0) HSA[4] (0) HEA[4] (0) VSA[4] (0) VEA[4] (1) 0 0 0 0 0 0 0 0 0 0 NL[4] (0) 0 BSA[4] (0) BEA[4] (1) VL[4] (0) ESA[4] (0) EEA[4] (0) ODP0[4] (0) OSA0[4] (0) OEA0[4] (0) ODP1[4] (0) OSA1[4] (0) OEA1[4] (0) ODP2[4] (0) OSA2[4] (0) OEA2[4] (0) 0 Setting Disabled Power Control (1) 0 0 0 0 0 1** Power Control System (Gate Driver / Power Supply IC Interface) 100h 102h-10Fh 110h Setting Disabled Gate Driver / Power Supply IC I/F Control (1) Gate Driver / Power Supply IC 111h I/F Control (2) 112h-1FFh Setting Disabled 200h 201h 202h 203h 204h 205h-20Fh RAM Address Set (1) RAM Address Set (2) RAM Data Write / Read RAM Write Data Mask (1) RAM Write Data Mask (2) Setting Disabled Horizontal RAM Address Poseition (1) Horizontal RAM Address Poseition (2) Vertical RAM Address Poseition (1) Vertical RAM Address Poseition (2) Setting Disabled Control (1) Control (2) Control (3) Control (4) Control (5) Control (6) Control (7) Control (8) Control (9) Control (10) Setting Disabled Line Number Control Screen Control Base Picture RAM Area (Start Line) Base Picture RAM Area (End Line) Vertical Scroll Control 0 0 0 TB[12] (0) 0 0 0 TB[11] (0) 0 0 0 TB[7] (0) AD[7] (0) AD[15] (0) 0 TB[3] (0) AD[3] (0) AD[11] (0) WM[3] (0) WM[15] (0) HSA[3] (0) HEA[3] (1) VSA[3] (0) VEA[3] (1) 0 0 0 0 VRP0[3] (0) 0 0 0 0 VRN0[3] (0) NL[3] (0) 0 BSA[3] (0) BEA[3] (1) VL[3] (0) ESA[3] (0) EEA[3] (0) ODP0[3] (0) OSA0[3] (0) OEA0[3] (0) ODP1[3] (0) OSA1[3] (0) OEA1[3] (0) ODP2[3] (0) OSA2[3] (0) OEA2[3] (0) 2** RAM Access System 0 0 0 0 0 0 RAM Write Data WD17-0 or RAM Read Data (RD17-0) Bit assignment will change according to the selected interface. 0 0 0 0 WM[11] (0) 0 WM[10] (0) 0 WM[9] (0) 0 WM[8] (0) 0 WM[7] (0) 0 0 0 HSA[7] (0) HEA[7] (1) VSA[7] (0) VEA[7] (0) 0 0 0 0 0 0 0 0 0 0 0 0 HSA[6] (0) HEA[6] (1) VSA[6] (0) VEA[6] (0) 0 0 0 0 0 0 0 0 0 0 Window Address Control System 210h 211h 212h 213h 214h-2FFh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKP1[2] (0) PKP3[2] (0) PKP5[2] (0) PRP1[2] (0) VRP1[2] (0) PKN1[2] (0) PKN3[2] (0) PKN5[2] (0) PRN1[2] (0) VRN1[2] (0) 0 0 0 0 0 0 0 0 0 0 0 PKP1[1] (0) PKP3[1] (0) PKP5[1] (0) PRP1[1] (0) VRP1[1] (0) PKN1[1] (0) PKN3[1] (0) PKN5[1] (0) PRN1[1] (0) VRN1[1] (0) 0 0 0 0 0 0 0 0 0 VSA[8] (0) VEA[8] (1) PKP1[0] (0) PKP3[0] (0) PKP5[0] (0) PRP1[0] (0) VRP1[0] (0) PKN1[0] (0) PKN3[0] (0) PKN5[0] (0) PRN1[0] (0) VRN1[0] (0) 0 0 BSA[8] (0) BEA[8] (1) VL[8] (0) ESA[8] (0) EEA[8] (0) ODP0[8] (0) OSA0[8] (0) OEA0[8] (0) ODP1[8] (0) OSA1[8] (0) OEA1[8] (0) ODP2[8] (0) OSA2[8] (0) OEA2[8] (0) 3** Control 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah-3FFh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRP1[4] (0) 0 0 0 0 VRN1[4] (0) 0 0 0 0 0 0 0 0 0 0 0 VRP1[3] (0) 0 0 0 0 VRN1[3] (0) 0 0 0 0 0 0 0 4** Coordinate Control System 400 401h 402h 403h 404h 405h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSA[7] (0) BEA[7] (0) VL[7] (0) ESA[7] (0) EEA[7] (0) ODP0[7] (0) OSA0[7] (0) OEA0[7] (0) ODP1[7] (0) OSA1[7] (0) OEA1[7] (0) ODP2[7] (0) OSA2[7] (0) OEA2[7] (0) 0 0 BSA[6] (0) BEA[6] (0) VL[6] (0) ESA[6] (0) EEA[6] (0) ODP0[6] (0) OSA0[6] (0) OEA0[6] (0) ODP1[6] (0) OSA1[6] (0) OEA1[6] (0) ODP2[6] (0) OSA2[6] (0) OEA2[6] (0) Base Picture 1RAM Magnified Area (Start Line) Base Picture 2RAM Magnified 406h Area (End Line) 407h-4FFh Setting Disabled 5** OSD Control 500h 501h 502h 503h 504h 505h 506h 507h 508h 6** 509h-5FFh 600h-6FFh OSD Picture 1 Display Position OSD Picture RAM Area Start Line OSD Picture 1 RAM Area End Line OSD Picture 2 Display Position OSD Picture 2 RAM Area Start Line OSD Picture 2 RAM Area End Line OSD Picture 3 Display Position OSD Picture 3 RAM Area Start Line OSD Picture 3 RAM Area End Line Setting Disabled Setting Disabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1) Numerals in parentheses in instruction bit cells are initial value. Note 2) Do not try to access to the index where setting is disabled. Rev.0.5, July.31.2003, page 96 of 196 HD66781 HD66783 Instruction Table IDX[2] IDX[1] IDX[0] TB[12] TB[11] GON DK DC1[1] TB[10] VCOMG TB[9] BT[2] EQM VDV[4] TB[8] BT[1] TB[7] BT[0] PON VDV[2] TB[6] DC0[2] VRH[3] VDV[1] Setting Disabled Setting Disabled Setting Disabled GS 0 NL[5] 0 NL[4] 0 NL[3] 0 NL[2] 0 NL[1] 0 NL[0] 0 SCN[5] 0 SCN[4] 0 SCN[3] 0 SCN[2] 0 SCN[1] FLD[1] TB[5] DC0[1] VRH[2] VDV[0] TB[4] DC0[0] VRH[1] VCM[4] TB[3] AP[2] VRH[0] VCM[3] TB[2] AP[1] VC[2] VCM[2] TB[1] AP[0] VC[1] VCM[1] Preliminary TB[0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 DC1[2] 0 VC[0] VCM[0] 1 DC1[0] 0 VDV[3] SCN[0] FLD[0] HD667P21 Instruction Table IDX[2] IDX[1] IDX[0] TB[12] TB[11] GON TB[10] VCOMG TB[9] BT[2] TB[8] BT[1] TB[7] BT[0] PON TB[6] DC[2] VRH[3] TB[5] DC[1] VRH[2] TB[4] DC[0] VRH[1] TB[3] AP[2] VRH[0] TB[2] AP[1] VC[2] TB[1] AP[0] VC[1] TB[0] 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 VC[0] 0 1 0 0 0 0 0 DK[1] VDV[4] 0 DK[0] VDV[3] 0 VDV[2] 0 VDV[1] Setting Disabled Setting Disabled Setting Disabled Setting Disabled 0 VDV[0] 0 VCM[4] 0 VCM[3] 0 VCM[2] 0 VCM[1] 0 VCM[0] 0 0 VGL[4] VGL[3] VGL[2] VGL[1] VGL[0] 0 VGH[4] VGH[3] VGH[2] VGH[1] VGH[0] AP and NL require a same and separate setting for each HD66781 and the register to transfer (Different Setting Disabled). 1. Setting for AP register of 781 2 Setting for AP register of 783/7P21 (R111h,TB[3]-[1]) 3 Serial Transfer to 783/7P21 (IDX000) Setting for NL register of 781 2 Setting for NL register of 783 (R111h 3 Serial Transfer to 783 (IDX110) Setting for FLD register of 781 2 Setting for FLD register of 783 (R111h 3 Serial Transfer to 783 (IDX111) TB[11]-[6]) TB[1]-[0]) Rev.0.5, July.31.2003, page 97 of 196 HD66781 Preliminary Reset Function The HD66781 is internally initialized by RESET input. During the reset period, internal settings are initialized. No access to instructions or GRAM data from the MPU is accepted during the reset period. The gate driver and the power supply are also automatically initialized when RESET input enters into the HD66781. The RESET period must be secured for at least 1 ms. In case of resetting by turning on the power supply (power-on reset), wait until the R-C oscillation frequency becomes stable after power is supplied (10 ms). During this period, do not access GRAM or make any initial instruction setting. Instruction Set Initialization See the parenthetic number in each bit in the instruction list for the initial value. RAM Data Initialization The RAM data are not automatically initialized by RESET input and must be initialized by software during the display-off period (D1-0 = 00). Output Pin Initialization 1. 2. 3. LCD driver output pins (source outputs) Vcom Gate driver control signal : Output GND level (All pins) : Halt (Output GND) : Halt (Output GND) (FLM1, FLM2, CL11/SFTCLK11, CL12/SFTCLK12, SFTCLK21, SFTCLK22, M1, M2, DISPTMG1, DISPTMG2, EQ1, EQ2, DCCLK1, DCCLK2) : Halt GCS, GCL, GDA (Vcc1 output) : Oscillate : Output GND : Same polarity with the RESET* input 4. 5. 6. 7. Gate driver serial interface Oscillator output pin Synchronizing signal (BST) RESET signal output Rev.0.5, July.31.2003, page 98 of 196 HD66781 Preliminary RAM Address and Display Position on the Panel The HD66781 incorporates a memory for 240RGB x 416-line display, and enables to drive QVGA-size panel (240RGB x 320 lines). Unused display memory is available for a partial OSD area. These features realize various ways of display with a single chip. The HD66781 allows independent settings for the display panel and the drive position, where the RAM area of each image is specified in relation to the display panel that is assigned to gate pins to fit into the assembly. Accordingly, in designing a panel, it is not necessary to take the assembly position into account. The HD66781 allows realizes various ways of display with the following settings: 1. 2. 3. 4. 5. Specify the RAM area of a base image (BSA, BEA) Specify the RAM area of an OSD image (OSAx, OEAx) Specify the display position of the OSD image (step 2) on the panel (ODPx). Specify the gate pins for driving the panel displaying a base image (SCN, NL) and the scan order (GS). Execute display ENABLE (BASEE, OSDE0/1/2) for each image after turning on display. A base image is a display that is set to be a basic display on each panel. An OSD image is a picture that is set to display on the base image. The panel-drive settings are made with gate scan starting position (SCN), the number of raster-rows to drive (NL), and scan direction (GS). The gate scan direction can be set differently for each panel to fit into the assembly. To change the display position horizontally, the setting of SS bit is required during RAM write. Table 53 Display ENABLE (Base image 1) BASEE Numbers of lines NL RAM area (BSA, BEA) Note 1) The base image is displayed from the start line of each panel. Note 2) Make sure that base image RAM area is NL BEA - BSA. Table 54 Display ENABLE OSD image 1 OSD image 2 OSD image 3 OSDE0 OSDE1 OSDE2 Display position ODP0 ODP1 ODP2 RAM area (OSA0, OEA0) (OSA1, OEA1) (OSA2, OEA2) Rev.0.5, July.31.2003, page 99 of 196 HD66781 Panel position Base image RAM address OSD image RAM address O SD Preliminary RAM write Address (HSA,HEA) im Gate pins n+1 SCN ODP0 BSA OSA0 1 ag e LCD Base image O OEA0 Window Address n+m GS SD im ODP1 OSA1 (VSA,VEA) 2 ag e O SD OEA1 ODP2 BEA NL+SCN OSA2 3 im ag e OEA2 RAM Address, display position and drive position Notes to the setting of panel control registers The HD66781 has some constrains in setting the coordinate with regard to the display data, position, and OSD. Screen settings The following equation must be observed in making a setting for the screen. NL 320 lines 0 SCN < SCN+NL 320 lines Base image display Base image is displayed from the first line of each panel. Base image display start position: SCN = BSA Set the base image RAM area (BSA, BEA) equal to or more than the number of lines (NL) required driving a panel. NL BEA - BSA OSD image display Set the OSD image RAM area (OSAx, OEAx) not to overlap one another. Set the OSD positions not to overlap one another. 0 ODP0 ODP0+ n x (OEA0 - OSA0+1) - 1< ODP1 ODP1+ n x (OEA1 - OSA1+1) - 1< ODP2 ODP2+ n x (OEA2 - OSA2+1) - 1 NL n: OSD image magnification scale The OSD images are displayed 100% when base image is turned off (BASEE = 0). The arrangement of channels is also changed when changing RGB order to BGR. The OSD data are read out in the format when ODF is set to 0. During interlaced drive (FLD = 2'h3), OSD and blending functions are not available. Rev.0.5, July.31.2003, page 100 of 196 HD66781 Preliminary Following figure shows the relationship among RAM address, display position, and panel drive. LCD panel physical line address G1 G2 G3 G4 G5 RAM line address 9'h000 SCN Display panel 0(1line) 1(2lines) 2(3lines) ODP0 OSD image 1 display area BSA ODP1 NL ( n line) GS OSD image 2 display area Base image RAM area ODP2 OSD image 3 display area n-1 BEA OSA0 OSD image RAM area OEA0 OSA1 G317 G318 G319 G320 OSD image RAM area OEA1 OSA2 OSD image RAM area OEA2 9'h19F Note: This figure shows the definition of address in relation to a display. The address for writing RAM data is defined by the window address. Display RAM address and panel display position Rev.0.5, July.31.2003, page 101 of 196 HD66781 Preliminary OSD and blending functions The HD66781 incorporates OSD and blending functions. The OSD image data has 3 bits to select transmission rates among 0, 25, 50, 75, 100%. The HD66781 not only handles 32,678-color OSD at maximum but also enables picture display data as OSD, in addition to usual single color text display. The HD66781 realizes various ways of display with a single-chip configuration. The HD66781 eliminates the processing of OSD and blending from the microcomputer. Just transmitting OSD image data including bits into the LCD driver as usual enables OSD and blending display. OSD and blending processing The HD66781 writes data to RAM as an OSD image according to the setting of OSD bit. An image read out as OSD according to the OSD image display setting is displayed after being processed according to the transmission rate set by bits. OSD and blending settings can be made by pixels (RGB). Table 55 2 1 0 Transmission rate Picture processing (Display data) Picture processing (Display data) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0% 25% 75% 50% 100% - Base image display Setting disabled Base image (75%) + OSD image (25%) display Base image (25%) + OSD image (75%) display Base image (50%) + OSD image (50%) display Setting disabled OSD image display Setting disabled Base image x 1.0 + OSD image x 0 25% transmission 75% transmission Base image x 0.5 + OSD image x 0.5 Base image x 0 + OSD image x 1.0 - Note 1) The OSD image is displayed 100% when base image is turned off (BASEE = 0). Rev.0.5, July.31.2003, page 102 of 196 HD66781 OSD and blending processing Preliminary The following is an example of display with OSD and blending functions with the HD66781. In the following example, the unused RAM area, which is not used for base image display, is used for OSD and blending RAM area. HD66781 RAM data H D66781 first panel di spla y First panel base i mage ar ea 100%OSD di spl ay icon 50%OSD display (Base color: yellow) 100% OSD display (letters) Fir st OSD image ar ea Second OSD i mage ar ea 100 % OSD di spl ay(icon) Thir d OSD i mage ar ea Display with OSD and blending OSD image data format OSD image data format ( bit arrangement) is changeable with ODF bits. Select an appropriate format for the system to process. When writing an OSD image to RAM, set OSD to 1 beforehand. Specify the RAM write area by the window address. OSD image data format ODF 0 1 Normal data D 17 R5 2 R5 D 16 R4 1 R4 D 15 R3 0 R3 D 14 R2 R4 R2 D 13 R1 R3 R1 D 12 2 R2 R0 D 11 G5 R1 G5 D 10 G4 R0 G4 D9 G3 G4 G3 D8 G2 G3 G2 D7 G1 G2 G1 D6 1 G1 G0 D5 B5 G0 B5 D4 B4 B4 B4 D3 B3 B3 B3 D2 B2 B2 B2 D1 B1 B1 B1 D0 0 B0 B0 OSD image display setting To make a setting for OSD image display, 1. Specify OSD RAM area (OSA, OEA) 2. Specify OSD position 3. Set OSD ENABLE (OSDE) Rev.0.5, July.31.2003, page 103 of 196 HD66781 Panel position Base image RAM address OSD image RAM address O SD Preliminary RAM write Address (HSA,HEA) im Gate pins n+1 SCN ODP0 BSA OSA0 1 ag e LCD Base image O OEA0 Window Address n+m GS SD im ODP1 OSA1 (VSA,VEA) 2 ag e O SD OEA1 ODP2 BEA NL+SCN OSA2 3 im ag e OEA2 RAM Address, display position, drive position Whenever making an OSD image setting, the following must be observed. 1. 2. Set the OSD RAM area with OSAx, OEAx not to overlap one another. Set the OSD position so that an OSD image does not overlap one another. 0 ODP0 ODP0+n x (OEA0 - OSA0+1) -1 < ODP1 ODP1+ n x (OEA1 - OSA1+1) -1 < ODP2 ODP2+ n x (OEA2 - OSA2+1) -1 NL "n" is a magnification scale of an OSD image. 3. 4. An OSD image is displayed 100% when the base image is turned off (BASEE = 0). During the interlaced drive (FLD = 2'h3), the OSD and blending functions are not available. OSD Setting(OSD,ODF) Address Set RAM data write OSD data write flow Rev.0.5, July.31.2003, page 104 of 196 HD66781 Preliminary Resizing function The HD66781 incorporates resizing function (contraction: x 1/2, x 1/4, magnification: x2) available when writing picture data. Contraction The HD66781 enables to write resized image data to RAM by simply transmitting original image data to the window address as usual with the setting of RSR bit that specifies the contraction rate. This means the HD66781 allows the system simply to transmit data as usual even if resizing is required, and therefore makes resized images easily available on cameras, sub panels, or as a thumbnail display of a picture. The HD66781 performs contraction resizing simply by selecting pixels. The resized image may seem distorted from the original image. Check the resized image before use. Transmitted image data 0 0 1 2 3 4 5 6 (0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0) 1 (0,1) (1,1) (2,1) (3,1) (4,1) (5,1) (6,1) 2 (0,2) (1,2) (2,2) (3,2) (4,2) (5,2) (6,2) 3 (0,3) (1,3) (2,3) (3,3) (4,3) (5,3) (6,3) 4 (0,4) (1,4) (2,4) (3,4) (4,4) (5,4) (6,4) 5 (0,5) (1,5) (2,5) (3,5) (4,5) (5,5) (6,5) 6 (0,6) (1,6) (2,6) (3,6) (4,6) (5,6) (6,6) RAM data 1/2 resizing 0 0 1 2 3 (0,0) (2,0) (4,0) (6,0) 1 (0,2) (2,2) (4,2) (6,2) 2 (0,4) (2,4) (4,4) (6,4) 3 (0,6) (2,6) (4,6) (6,6) Resizing: contraction transmitted data for RAM write Main Panel Display HD66781 RAM data 240 RSZ=2'h1 66 160 320 RAM Write Resizing transmission, display example Table 56 Original image size (X x Y) 640x480(VGA) 352x268 (CIF) 320x240 (QVGA) 176x144 (QCIF) 120x160 132x176 1/2 (RSZ = 2'h1) 320x240 176x144 160x120 88x72 60x80 66x88 Resized image size 1/4 (RSZ = 2'h3) 160x120 88x72 80x60 44x36 30x40 33x44 Rev.0.5, July.31.2003, page 105 of 196 HD66781 Resizing setting Preliminary The HD66781 selects resizing (contraction) rate according to the setting of RSR bit. Specify the RAM window-address range to fit into the resized picture. If resizing creates surplus pixels according to the result of calculation using the following formulas, set them in RCV, RCH registers before writing data to RAM. HD66781 GRAM Address X (X0,Y0) Formulas for calculating the number of surplus pixels Rx The number of surplus pixels in horizontal direction L = X mod N Y Original image data size Ry RAM write data (1/N resizing) The number of surplus pixels in vertical direction M = Y mod N Resized picture size in horizontal direction (X0+Rx-1,Y0+Ry-1) Rx = (X-L)/N Resized picture size in vertical direction Ry = (Y-M)/N Resizing Setting, surplus pixel calculation Table 57 Original image (before resizing) number of data in horizontal direction number of data in vertical direction resizing ratio X Y 1/N HD66781 settings Resizing setting number of data in horizontal direction number of data in vertical direction RAM writing start address RAM window address RSR RCV RCH AD HSA HEA VSA VEA N-1 L M (X0, Y0) X0 X0+Rx - 1 Y0 Y0+Ry - 1 HD66781 GRAM address X=240 (0,0) Rx=120 RAM write data (1/2 resizing) 120 x 160 Ry=160 Y=320 Original image data 240 x 320 (119,159) Resizing setting example (1/2 size) Rev.0.5, July.31.2003, page 106 of 196 HD66781 Table 58 Original image (before resizing) number of data in horizontal direction number of data in vertical direction resizing ratio X Y 1/N 240 320 1/2 Preliminary HD66781 settings Resizing setting number of data in horizontal direction number of data in vertical direction RAM writing start address RAM window address RSR RCV RCH AD HSA HEA VSA VEA 2'h1 2'h0 2'h0 17'h00000 8'h00 8'h77 8'h00 8'h9F Instructions for Resizing Table 59 RSR[1:0] 2h'0 2h'1 2h'2 2h'3 Resizing ratio ratio No resizing (x 1) 1/2 resizing (x 1/2) setting disabled 1/4 resizing (x 1/4) Table 60 Surplus pixels horizontal direction RCH[1:0] 2h'0 2h'1 2h'2 2h'3 1 pixel = 1 RGB vertical direction RCV[1:0] 2h'0 2h'1 2h'2 2h'3 1 pixel = 1 RGB surplus pixels 0 1 pixel 2 pixels 3 pixels surplus pixels 0 1 pixel 2 pixels 3 pixels Rev.0.5, July.31.2003, page 107 of 196 HD66781 Notes to the resizing function 1. 2. 3. 4. 5. Preliminary Make settings for resizing instructions (RSR, RCV, and RCH) before writing data to RAM. Write data to RAM from the start position of the window address by line when using resizing function. Fit the window-address range into the size of the resized picture. Make an address set before writing data to RAM when using resizing function. Settings for RCH, RCV are only required when using resizing function. Otherwise (RSR = 2'h0), set RCH = RCV = 2'h0. Res i zi n g set t i n g (RSR, RCH,RCV) Wi ndow addr ess sett i ng (HSA , H SE, VSA, VE A) Addr ess set RAM dat a wr it e Note: The window-address range must be fit into the size of a resized image RAM Writing flow when using resizing Rev.0.5, July.31.2003, page 108 of 196 HD66781 Magnification Preliminary The HD66781 enables to write resized image data to RAM by simply transmitting original image data to the window address as usual with the settings of RESH/RESEV[7:0] bits that specify the magnification rate each for the base and OSD images. The magnification rate is specified each for the base and OSD images. Also, only a part of RAM area of a base image can be magnified on display in the vertical direction. This means the HD66781 allows the system simply to transmit an original data as usual even when displaying a magnified image on a large screen, and therefore enables to reduce the data transmission required for a large screen display. The display magnification in the vertical direction should be specified by line. Base image: The image specified by ESA[8:0] and EEA[8:0] on RAM is magnified on display by the scale set by the RSEV[1:0] setting. OSD image: The image specified by OSAx[8:0] and OEAx[8:0] on RAM is magnified on display in the manner set by the RSEV[7:2] setting. When magnifying in the horizontal direction, the window-address settings (HSA[0], HEA[0]), RAM address set (AD[0]), and horizontal incremental direction of the counter (I/D[0]) as follows. Table 61 Registers HSA[0] HEA[0] AD[0] Register setting 1'b0 1'b1 1'b0 when I/D[0]=0 1'b1 when I/D[0]=1 The HD66781 performs magnification resizing simply by inserting pixels. The resized image is an extended original image in both horizontal and vertical direction. Check the resized image before use. data of an image to transfer 0 0 1 2 3 (0,0) (1,0) (2,0) (3,0) 1 (0,1) (1,1) (2,1) (3,1) 2 (0,2) (1,2) (2,2) (3,2) 3 (0,3) (1,3) (2,3) (3,3) 0 1 (0,0) (1,0) (2,0) (3,0) 2 (0,1) (1,1) (2,1) (3,1) 0 1 2 3 (0,0) (1,0) (2,0) (3,0) RAM data 3 (0,1) (1,1) (2,1) (3,1) 4 (0,2) (1,2) (2,2) (3,2) 5 (0,2) (1,2) (2,2) (3,2) 6 (0,3) (1,3) (2,3) (3,3) 7 (0,3) (1,3) (2,3) (3,3) Horizontal direction x2 resizing RSEH=1 vertical direction x2 resizing RSEV=1 Display on the panel 1 2 3 4 5 6 7 (0,0) (1,0) (1,0) (2,0) (2,0) (3,0) (3,0) (0,0) (1,0) (1,0) (2,0) (2,0) (3,0) (3,0) (0,1) (1,1) (1,1) (2,1) (2,1) (3,1) (3,1) (0,1) (1,1) (1,1) (2,1) (2,1) (3,1) (3,1) (0,2) (1,2) (1,2) (2,2) (2,2) (3,2) (3,2) (0,2) (1,2) (1,2) (2,2) (2,2) (3,2) (3,2) (0,3) (1,3) (1,3) (2,3) (2,3) (3,3) (3,3) (0,3) (1,3) (1,3) (2,3) (2,3) (3,3) (3,3) Resizing: magnification Rev.0.5, July.31.2003, page 109 of 196 HD66781 Preliminary The following figure illustrates the relationship of RAM address, display position and panel driving position when a base image is magnified in the vertical direction. RESV[1:0] = 2'h1 LCD panel physical line address RAM line address 9'h000 Display panel 0(1line) 0(1line) 1(2lines) 2(3lines) BSA (ESA - BSA) (ESA - BSA) (ESA - BSA +1) (ESA - BSA +1) NL ESA 2 Base image RAM magnified display area (EEA - BSA - 1) (EEA - BSA - 1) (EEA - BSA) (EEA - BSA) (EEA - BSA + 1) n-1 Base image RAM magnified area EEA EEA + 1 Base image RAM area BEA Note 1) BSA ESA EEA BEA Note 2) The RAM area of a base image outside the NL range is not displayed on a panel. 9'h19F Rev.0.5, July.31.2003, page 110 of 196 HD66781 RSEV[3:2] = 2'h1, RSEV[5:4] = 2'h0, RSEV[7:6] = 2'h0 9'h000 Preliminary 0(1line) 0(1line) 1(2lines) 2(3lines) ODP0 BSA OSD image 1 magnified display area OSD image 1 display area (OEA0 - OSA0 +1) 2 lines ODP1 OSD image 2 display area BEA ODP2 OSD image 3 display area n-1 OSA0 OSD image 1 RAM area OEA0 OSA1 OSD image 2 RAM area OEA1 OSA2 OSD image 3 RAM area OEA2 9'h19F Note: The OSD display positions must be designated not to overlap one another. 0 ODP0 ODP0 +n ODP1 ODP1 +n ODP2 ODP2 +n (OEA0-OSA0+1) - 1 (OEA1-OSA1+1) - 1 (OEA2-OSA2+1) - 1 NL n: magnification scale of OSD display Rev.0.5, July.31.2003, page 111 of 196 HD66781 Preliminary Interface specification The HD66781 incorporates a system interface to make settings for instructions and an external display interface to display moving pictures. The HD66781 allows selecting an optimum interface for display (moving or still picture, or both) to transmit data efficiently. The external display interface includes RGB interface and VSYNC interface, which enable flicker-free screen update. In the RGB-I/F mode, the display operation is performed in synchronization with the signals (VSYNC, HSYNC, and DOTCLK). The display data are written according to the values of the data enable signal (ENABLE), and PD17-0 bits in synchronization with the VSYNC, HSYNC, and DOTCLK signals. The display data are written to GRAM to reduce the data transmission to minimum, i.e. only when the displays are being changed. With the window address function, only the RAM area used for moving picture display is overwritten, and therefore the simultaneous display of moving picture area, which is overwritten, and the RAM data in the area other than the moving picture area, which is not overwritten, is possible. In the RGB and VSYNC interface modes, write data to GRAM in the high speed write mode (HWM = 1) during displaying moving pictures to access to GRAM in high speed with low power consumption. In the VSYNC interface mode, the frame synchronization signal (VSYNC) synchronizes internal display operations. By writing data in synchronization with the falling edge of VSYNC at a fixed speed to GRAM through a system interface, moving pictures are displayed with the system interface in use. In this case, there are some constraints in the speed and method to write data to RAM. The HD66781 handles the following 4 operational modes according to the type of display. All settings are made through the external display interface. Transition between the modes must be done according to the transitional flow charts. Table 62 Operation Mode Internal operating clock only (Displaying still picture) RGB interface (1) (Displaying moving picture) RGB interface (2) (Rewriting still picture while displaying moving pictures) VSYNC interface (Displaying moving pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM1-0) Internal operating clock (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10) Note 1) Instructions are set only through a system interface. Note 2) RGB-I/F and VSYNC-I/F are not used simultaneously. Note 3) Do not make a change to the RGB-I/F mode (RIM-0) while the RGB I/F is operating. Note 4) When making transitions between the interfaces, see the "External Display Interface" (p.139) for the transition flow chart Note 5) RGB-I/F and VSYNC-I/F modes should be used with the high-speed write mode (HWM = 1). Rev.0.5, July.31.2003, page 112 of 196 HD66781 Preliminary CS* RS System interface WR* (RD*) DB17-0 18/16/9/8 System HD66781 ENABLE VSYNC RGB interface HSYNC DOTCLK PD17-0 18/16/6 HD66781 Interface Rev.0.5, July.31.2003, page 113 of 196 HD66781 Preliminary System Interface The setting with IM3/2/1/0 pins allows selecting among the following system interfaces. The system interface enables instruction settings and RAM access. Table 63 IM3 0 0 0 IM bits settings and system interface IM1 0 0 1 IM2 0 0 0 IM0 0 1 0 Interfacing mode with MPU Setting disabled Setting disabled 80-system 16-bit interface DB Pin Colors DB17 to 10 and 8 to 1 65,536 (262,144) Note 2) 0 0 1 1 80-system 8-bit interface (Big endian) DB17 to 10 65,536 (262,144) Note 2) 0 0 0 1 1 1 0 1 1 * 0 1 Serial Peripheral interface (SPI) Setting disabled 80-system 8-bit interface (Little endian) DB1 to 0 65,536 DB17 to 10 65,536 (262,144) Note 2) 1 1 1 1 1 0 0 0 0 1 0 0 1 1 * 0 1 0 1 * Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17 to 0 DB17 to 9 262,144 262,144 Note 1) 262,144 colors in 16-bit data bus 2-transmission mode. Note 2) 262,144 colors in 8-bit data bus 3-transmission mode. Rev.0.5, July.31.2003, page 114 of 196 HD66781 80-system 18-bit interface Preliminary 80-system 18-bit parallel data transmission is selected by setting IM3/2/1/0 pins to Vcc1/GND/Vcc1/GND levels. CSn* A1 CS* RS WR* (RD*) DB17-0 MPU HWR (RD*) D31-0 HD66781 18 Example of Interface with the 18-bit Microcomputer Instruction input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 Instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 GRAM write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1 pixel In 18-bit interface mode, Normal display: 262,144 colors OSD display: 32,768 colors 18-bit interface data format (Instruction / RAM write data) Rev.0.5, July.31.2003, page 115 of 196 HD66781 80-system 16-bit interface Preliminary 80-system 16-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/GND/Vcc1/GND levels. CSn* A1 CS* RS WR* (RD*) DB17-10,8-1 MPU HWR (RD*) D15-0 HD66781 16 16-bit microcomputer and interface (example) Instruction Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 Instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1pixel 65,536 Color with 16-bit system interface input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1pixel 8,192 Color with 16-bit system interface input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 OSD data ODF=1 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 Color with 16-bit system interface 16-bit interface data format (Instruction / RAM write data) Rev.0.5, July.31.2003, page 116 of 196 HD66781 80 system 16 bit interface (2 transmissions: TRI = 1, DFM = 0) 1st transmission DB DB DB 8 11 10 Preliminary 2nd transmission GRAM data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 DB 16 RGB Assignment WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] GRAM write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1 pixel Note: Normal display in 262,144 colors, OSD display in 32,768 colors in16-bit system interface, 2-transmission mode. 80 system 16 bit interface (2 transmissions: TRI =1, DFM = 1) 1st transmission GRAM data DB 2 DB 1 DB 17 DB 16 2nd transmission DB DB DB DB 14 13 12 15 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RGB Assignment WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] GRAM write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1 pixel Note: Normal display in 262,144 colors, OSD display in 32,768 colors in16-bit system interface, 2-transmission mode. 16-bit interface data format (RAM write data in 2-transmission mode) Rev.0.5, July.31.2003, page 117 of 196 HD66781 Data transmission synchronization in 16-bit bus interface mode Preliminary The HD66781 supports the data transmission synchronization function, which resets the counter that counts the number of data transmission of upper 2 bits and lower 16 bits or upper 16 bits and lower 2 bits in the 16-bit data bus interface 2-transmission mode. When a discrepancy occurs in the data transmission of the upper/lower bits due to effects from noise and so on, the "000" H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. RS RD WR DB17~10 DB8~1 Upper Lower "000"H "000"H "000"H "000"H Upper Lower Upper (16-bit transmission synchronization) Data Transmission Synchronization Rev.0.5, July.31.2003, page 118 of 196 HD66781 80-system 9-bit interface Preliminary The 80-system 9-bit parallel data transmission through DB17-9 pins is selected by setting IM3/2/1/0 pins to Vcc1/GND/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits (the LSB is not used) and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 9 bits, and the upper bits are transmitted first. The DB8-0 pins, that are not used, must be fixed to either IOVcc level. When writing the index register, the upper byte (8 bits) must be written. CSn* A1 CS* RS WR* (RD*) DB17-9 H8/2245 HWR (RD*) D15-0 HD66781 9 9 DB8-0 Example of Interface with the 9-bit Microcomputer Instruction input DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 9 DB 17 DB 16 Second transmission (Lower) DB DB DB DB DB DB 15 14 13 12 11 10 DB 9 instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write Input DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 9 DB 17 DB 16 Second transmission (Lower) DB DB DB DB DB DB 14 13 12 11 10 15 DB 9 GRAM write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1pi xel with 9-bit system interface Normal display : 262,144 colors OSD : 32,768 colors 9-bit interface data format Rev.0.5, July.31.2003, page 119 of 196 HD66781 Data transmission synchronization in 9-bit bus interface mode Preliminary The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 9 bits in the 9-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 9 bits due to effects from noise and so on, the "000" H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 9-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. RS RD WR DB17~9 Upper Lower "000"H "000"H "000"H "000"H Upper Lower Upper (9- bit transmission synchronization) 9-bit Transfer Synchronization Rev.0.5, July.31.2003, page 120 of 196 HD66781 80-system 8-bit interface (Big endian) Preliminary The 80-system 8-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/GND/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into 18 bits internally. The DB9-0 pins, that are not used, must be fixed to either IOVcc level. When writing the index register, the upper byte (8 bits) must be written. CSn* A1 CS* RS WR* (RD*) DB17-10 H8/2245 HWR (RD*) D15-0 HD66781 8 10 DB9-0 Example of Interface with the 8-bit Microcomputer Rev.0.5, July.31.2003, page 121 of 196 HD66781 Instruction DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 IB 13 DB 17 DB 16 Preliminary Input Second transmission (Lower) DB DB DB DB DB DB 15 14 13 12 11 10 Instruction IB 15 IB 14 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write (2 transmission mode :TRI=0) Input DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 17 DB 16 Second transmission (Lower) DB DB DB DB DB DB 15 14 13 12 11 10 GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 1pixel 65,536 colors with 8-bit system interface Input DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 17 DB 16 Second transmission (Lower) DB DB DB DB DB DB 15 14 13 12 11 10 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1pixel 8,192 colors with 8-bit system interface Input DB 17 DB 16 First transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 17 DB 16 Second transmission (Lower) DB DB DB DB DB DB 15 14 13 12 11 10 OSD data ODF=0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface 8-bit interface data format, RAM data write (2-transmission mode) Rev.0.5, July.31.2003, page 122 of 196 HD66781 RAM data write(3 transmission mode : TRI =1, DFM =0) first transmission Preliminary input DB 11 DB 10 DB 17 DB 16 second transmission DB DB DB DB DB 15 14 13 12 11 DB 10 DB 17 DB 16 DB 15 third transmission DB DB DB 14 13 12 DB 11 DB 10 GRAM data write OSD data ODF=0 OSD data ODF=1 R5 R5 R4 R4 R3 R3 R2 R2 R5 R1 R1 R4 R0 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 2 R3 1 G2 0 B1 2 1 0 1 pixel with 8-bit system interface Normal display : 262,144 colors OSD : 32,786 colors RAM data write (3 transmission mode :TRI =1, DFM =1) DB 11 DB 10 first transmission DB DB DB 17 16 15 DB 14 DB 13 second transmission DB DB DB DB 17 12 11 10 DB 16 DB 15 DB 14 third transmission DB DB DB 13 12 11 DB 10 input GRAM data write OSD data ODF=0 OSD data ODF=1 R5 R5 R4 R4 R3 R3 R2 R2 R5 R1 R1 R4 R0 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 2 R3 1 G2 0 B1 2 1 0 1 pixel with 8-bit system interface Normal display : 262,144 colors OSD : 32,768 colors 8-bit interface data format, RAM data write (3-transmission mode) Rev.0.5, July.31.2003, page 123 of 196 HD66781 Data transmission synchronization in 8-bit bus interface mode Preliminary The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 8 bits in the 8-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 8 bits due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 8-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. RS RD WR DB17~10 Upper Lower "00"H "00"H "00"H "00"H Upper Lower Upper (8-bit transfer synchronization) 8-bit data transmission synchronization Rev.0.5, July.31.2003, page 124 of 196 HD66781 Serial Peripheral interface (SPI) Preliminary The Serial Peripheral Interface (SPI) is selected by setting IM3/2/1 pins to GND/Vcc1/GND levels respectively. The SPI is available through the chip select line (CS), serial transfer clock line (SCL), serial data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the SPI mode, the DB17-2 pins, which are not used, must be fixed at either IOVcc level. The HD66781 recognizes the start of data transfer at the falling edge of CS input to initiate the transfer of start byte. It recognizes the end of data transfer at the rising edge of CS input. The HD66781 is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66781 are compared and both 6-bit data correspond. When selected, the HD66781 starts taking in the subsequent data string. The setting for the least significant bit of the identification code is made with the ID pin. The five upper bits of the identification code must be 01110. Two different chip addresses must be assigned to the HD66781 because the seventh bit of the start byte is assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1. In the SPI mode, the data are written to GRAM after two-byte data transmission. The data are expanded into 18 bits by adding one bit (the same data as the MSB of RB) to the LSB of RB data. After receiving the start byte, the HD66781 starts to transmit or receive data by byte. The data transmission adopts a format by which the MSB is first transmitted. All HD66781 instructions consist of 16 bits and they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to write to RAM are expanded into 18-bit data. After the start byte is received, the first byte is always fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. The 4-byte data that are read from RAM right after the start byte are made invalid. The HD66781 reads as valid data from the 5th-byte data. Start Byte Format Transmitted bits Start byte format S Transmission start 1 2 3 4 5 6 7 RS 1 0 ID 8 R/W Device ID code 0 1 1 Note 1) ID bit is selected with the IM0/ID pin. Table 64 RS 0 0 1 1 R/W 0 1 0 1 Function Set index register Read status Write instruction or RAM data Read instruction or RAM data Rev.0.5, July.31.2003, page 125 of 196 HD66781 instruction input Preliminary D 15 D 14 D 13 First transmission (upper) D D D D9 D8 12 11 10 Second transmission (lower) D7 D6 D5 D4 D3 D2 D1 D0 instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write input DB 17 DB 16 First transmission (upper) DB DB DB DB DB DB 11 10 15 14 13 12 DB 8 DB 7 Second transmission (lower) DB DB DB DB DB DB 6 5 4 3 2 1 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 1pi xel 65,536 colors with serial interface input DB 17 DB 16 First transmission (upper) DB DB DB DB DB DB 14 13 12 11 10 15 DB 17 DB 16 Second transmission (lower) DB DB DB DB DB DB 14 13 12 11 10 15 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1pixel 8,192 colors with serial interface input DB 17 DB 16 First transmission (upper) DB DB DB DB DB DB 14 13 12 11 10 15 DB 17 DB 16 Second transmission (lower) DB DB DB DB DB DB 14 13 12 11 10 15 OSD data ODF=0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with serial interface Data format for Serial Peripheral Interface Rev.0.5, July.31.2003, page 126 of 196 HD66781 (a) Clock synchronization serial transmission (Basic) Transmission start CS input 1 SCL input MSB SDI input "0" "1" "1" "1" "0" ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Preliminary Transmission end Device ID code Start bite RS RW Index register set, instruction set, RAM data write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO output Status read, instruction read, RAM data read (b) Clock synchronization serial transmission (consecutive) CS input SCL input SDI input Start Start bite Instruction(1) Upper 8 bits Instruction(1) Lower 8 bits Instruction(2) Upper 8 bits Instruction(2) Lower 8 bits End The first bite right after start bite is always upper 8 bits Instruction (1) execution time (c) RAM read-out transmission CS input SCL input SDI input Start bite RS=1 R/W=1 SDO output Start dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 RAM read Upper 8 bits RAM read Lower 8 bits End The 5 bites right after start bite are dummy read, and invalid data are read out to RAM. Normal RAM data read starts from the 6th byte. (d) status read, instruction read CS input SCL input SDI input Start byte RS = 0 R/W = 1 SDO output Start dummy read 1 Status Read Upper 8 bits Status Read Lower 8 bits The 1 bite right after Start bite is dummy, and invalid data are read out to RAM. Normal RAM data read starts from the 2nd byte. End Serial Peripheral Interface: data transfer Rev.0.5, July.31.2003, page 127 of 196 HD66781 80-system 8-bit interface (Little endian) Preliminary The 80-system 8-bit parallel data transmission is selected by setting IM3/2/1/0 pins to GND/Vcc1/Vcc1/Vcc1 levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into 18 bits internally. The DB9-0 pins, that are not used, must be fixed to either IOVcc level. When writing into the index register, the upper byte (8 bits) must be written. CSn* A1 CS* RS WR* (RD*) DB17-10 H8/2245 HWR (RD*) D15-0 HD66781 8 10 DB9-0 Example of Interface with the 8-bit Microcomputer Rev.0.5, July.31.2003, page 128 of 196 HD66781 Instruction DB 17 DB 16 Second transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 Preliminary Input DB 17 DB 16 DB 15 First t ransmission (Lower) DB DB DB DB DB 14 13 12 11 10 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 instruction code IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write (2 transmission mode :TRI=0) Input DB 17 DB 16 Second transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 8 DB 7 DB 6 First t ransmission (Lower) DB DB DB DB DB 5 4 3 2 1 GRAM data write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1pixel 65,536 colors with 8-bit system interface Input DB 17 DB 16 Second transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 17 DB 16 DB 15 First t ransmission (Lower) DB DB DB DB DB 14 13 12 11 10 OSD data ODF=0 R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1pixel 8,192 colors with 8-bit system interface Input DB 17 DB 16 Second transmission (Upper) DB DB DB DB DB DB 15 14 13 12 11 10 DB 17 DB 16 DB 15 First transmission (Lower) DB DB DB DB DB 14 13 12 11 10 OSD data ODF=0 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1pixel 8,192 colors with 8-bit system interface 8-bit interface data format, RAM data write (2-transmission mode) Rev.0.5, July.31.2003, page 129 of 196 HD66781 Data transmission synchronization in 8-bit bus interface mode Preliminary The HD66781 supports the data transmission synchronization function, which resets the upper/lower counters that count the number of data transmission of upper/lower 8 bits in the 8-bit bus interface mode. When a discrepancy occurs in the data transmission of the upper/lower 8 bits due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to reset the upper/lower counters so that data transmission restarts with the upper 8-bit transmission. Periodical execution of synchronization function allows the display system to recover from excursion. RS RD WR DB17~10 Upper Lower "00"H "00"H "00"H "00"H Upper Lower Upper (8-bit transfer synchronization) 8-bit data transmission synchronization Rev.0.5, July.31.2003, page 130 of 196 HD66781 Preliminary DMA transfer Single Address mode When connecting a microcomputer or an application processor, which are compliant to DMA transfer single address mode, with the HD66781, and SRAM or pseudo SRAM, the HD66781 allows using same bus cycle for data read from memory and data write to the HD66781. This reduces transfer time and controls bus occupation ratio when transferring a large volume of data from external memory to a LCD driver. 1. Pin functions in DMA single address mode DACK: In DMA single address mode, it has the same function as CS in normal operation mode. RD: Recognize write strobe (WR) internally when DACK is at the low level (active). WR: Fix to High. CS: Fix to High. RS: Recognize a high level (data transfer) inside the HD66781 under any condition when DACK is at the low level (active). CSn* A21-0 1 CS* RS WR* RD* DB15-0 DACK* CS* AD21-0 WE* OE* D15-0 SH7300 WR RD* D15-0 DACK* CSm* HD66781 DREQ Rev.0.5, July.31.2003, page 131 of 196 Port SRAM Interfacing with microcomputer and SRAM HD66781 2. Transfer procedure in DMA single address mode Normal operation HWM=1,AM=0,I/D Set Window address set (HSA,HEA,VSA,VEA) Address set Index register set (R202h) Preliminary Settings for HD66781 Words for transfer Source address Transfer mode set Settings for DMAC DREQ (Transfer request signal) output Note 1) Detect DREQ signal Start transfer Data transfer Note 1) Set to level acceptance an output from an assigned control port, DREQ judgement End of transfer Transferred word counter=0 Release DREQ Normal operation Setting for DMAC Rev.0.5, July.31.2003, page 132 of 196 HD66781 3. Notes to the DMA single address mode 1. 2. 3. Preliminary 4. 5. 6. DACK*pin and CS*pin cannot be made at a low level (active) simultaneously. Once starting a transfer in the DMA single address mode, no command access to the HD66781 will be allowed until the end of the transfer. The DMA single adders mode must be used with the window address function to make sure the number of data transfer in the DMA mode and the numbers of data in the specified window address area correspond. . After transferring in the DMA mode, wait at least for RAM write execution time (bus cycle time in the normal write mode, tcycw) before issuing a next instruction. It is not possible to make a transfer form the HD66781 to external memory in the DMA single address mode. The DMA single address mode is compatible with the normal cycle still mode and the burst mode. Data transfer in DMA single address mode (cycle still mode) DREQ Bus cycle CPU CPU CPU DMAC R/W CPU DMAC R/W DMAC R/W CPU DMAC R/W CPU Data transfer in DMA single address mode (burst mode) DREQ Bus cycle CPU CPU CPU DMAC R/W DMAC R/W DMAC R/W DMAC R/W DMAC R/W DMAC R/W CPU Reference: Data transfer in DMA dual address mode (burst mode) DREQ Bus cycle CPU CPU CPU DMAC Read DMAC Write DMAC Read DMAC Write DMAC Read DMAC Write CPU Rev.0.5, July.31.2003, page 133 of 196 HD66781 Preliminary VSYNC Interface The HD66781 incorporates a VSYNC-I/F, which enables moving picture display with a system interface and the frame synchronization signal (VSYNC) only. This interface enables the display of moving pictures with minimum modification to the conventional system. VSYNC LCDC/MPU CS* RS WR* DB17-10,8-1 HD66781 16 VSYNC interface The VSYNC-I/F is selected by setting DM1-0 = 10 and RM = 0. In the VSYNC I/F mode, the internal display operations are synchronized with VSYNC. By writing data to RAM through the system interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it enables moving picture display through a system interface and flicker-free screen update. Display operations are executed by the internal clock generated by the internal oscillator and the VSYNC input. All display data are stored in RAM. Therefore, it only requires transfer of the data that is written over to update the screen, thereby minimizing the numbers of data transfers while displaying moving picture. The use of high-speed write mode (HWM = 1) with VSYNC interface enables RAM access in high speed with low power consumption. VSYNC System interface RAM data Write Display execution with internal clock Moving picture data transmission through VSYNC interface Note 1) Data must be written to RAM in the high-speed write mode (HWM = 1) in VSYNC interface mode. Rev.0.5, July.31.2003, page 134 of 196 HD66781 Preliminary The VSYNC-I/F has limits on the minimum speed for RAM write through the system interface and the frequency of the internal clock. It requires RAM write speed more than the calculated result from the following formula. Internal clock frequency (fosc) [Hz] = Frame frequency x (Display raster-row (NL) + Front porch (FP) +Back porch (BP)) x 16 clocks x Fluctuation RAM writing speed (min.) [Hz] > 320x Display lines (NL)/{[(Back porch (BP)+Display lines (NL) - margin) x 16 clocks] /fosc} When RAM write does not start immediately after the falling edge of VSYNC, the period from the falling edge of VSYNC to the start of RAM write must also be taken into consideration. An example of calculations for the internal clock frequency and RAM write speed in the VSYNC interface mode is as follows. * * * * Calculation Example: moving picture display in VSYNC I/F Panel size 240 RGB x 320 raster-rows (NL0 = 6'27) Total number of raster-rows(NL) 320 raster-rows Back, Front porches 14, 2, raster-rows (BP = 4'hE, FP = 4'h2) * Frame frequency 60Hz Internal clock frequency (fosc) Hz = 60 Hz x (320 + 2 + 14) raster-rows x 16 clocks x 1.1 / 0.9 = 394 [kHz] When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. The allowance for this fluctuation is 10 % from the center value, and the range of the frequency must be within the VSYNC cycle. As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room temperature into account. Other possible causes of fluctuations, such as variation in the external resistors or the voltage change are not considered in the above calculation. It is necessary to make a setting with enough margins to include the allowances for these factors. Minimum RAM writing speed [Hz] > 240 x 320 / {((14 + 320 - 2) raster-rows x 16 clocks) / 394 kHz} = 5.70 [MHz] In this case, RAM write is performed on the input of VSYNC. When the data for one frame are written to RAM completely, there must be 2 raster-rows or more of a margin before the display raster-rows. According to the above calculation results, writing data to RAM on the input of VSYNC at the speed of 5.7 MHz or more, the data for the entire screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to moving picture update can be avoided even if displaying a moving picture. Rev.0.5, July.31.2003, page 135 of 196 HD66781 VSYNC RAM write Back porch (14 lines) Display operation [lines] 320 RAM write (10MHz)76,800 times Preliminary R-C oscillation 10% FP=2H line processing RAM write 5.70MHz Display operation Panel Moving picture Display (320 lines) 0 BP=14H VSYNC 7.68 13.4 13.5 [ms] 16.67 (60Hz) Front porch (2 lines) Blank period Minimum RAM write speed and internal clock frequency in VSYNC interface Rev.0.5, July.31.2003, page 136 of 196 HD66781 Notes to the VSYNC interface 1. Preliminary The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations such as internal oscillators and so on should be taken into consideration. It is necessary to make a setting for RAM write speed with enough margins. The aforementioned example of calculation is the value in case of writing over the entire screen. Limiting the area for the moving picture display will create more margins for the RAM write speed. RAM write Display operation 2. [lines] 320 300 line processing R-C oscillation 10% Back porch (14 lines) FP=2H RAM write 5.70MHz Panel Moving picture Display (280 lines) Display operation Front porch (2 lines) Blank period VSYNC 20 0 BP=14H 11.8 13.4 [ms] 16.67 (60Hz) Condition on using VSYNC interface 3. 4. 5. 6. 7. A front porch period continues after the completion of 1 frame display and until the next input of VSYNC. The transition between the internal clock operation mode (DM1-0 = 00) and the VSYNC interface mode becomes effective after displaying one frame made during instruction setting. In the VSYNC interface mode, the partial display, vertical scroll, and interlaced drive functions are not available. In the VSYNC interface mode, set AM to 0 to transmit display data in the aforementioned method. In the VSYNC interface mode, write display data to RAM in the high speed write mode (HWM = 1) Rev.0.5, July.31.2003, page 137 of 196 HD66781 From Internal clock operation to VSYNC interface mode Internal clock operation HWM = 1, AM = 0 Address Setting VSYNC interface mode setting (DM1-0=10, RM=0) Index resister setting (R202)h Display operation in synchronization with the internal clocks Preliminary From VSYNC interface mode to Internal clock operation VSYNC interface operation Display operation in synchronization with VSYNC The settings in DM1-0, RM become valid after displaying one frame. Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame The settings in DM1-0, RM become valid after displaying one frame. Internal clock operation Display operation in synchronization with the internal clocks Wait more than 1 frame Note: VSYNC signal must be supplied for at least one frame when switching to the internal clock operation. VSYNC interface Writing RAM data Display operation in synchronization with VSYNC VSYNC interface operation Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame Internal clock operation Note: VSYNC signal must be supplied before setting DM1-0, RM when switching to the VSYNC I/F mode. Transition between VSYNC and Internal clock operation modes Rev.0.5, July.31.2003, page 138 of 196 HD66781 Preliminary External Display Interface The following interfaces are available as an external display interface (RGB interface). The interface is selected by setting RIM1-0 bits. The RGB interface allows RAM access. Table 65 RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface PD Pin 18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting disabled PD17-0 PD17-13, 11-1 PD17-12 - Note 1) It is not possible to use multiple interfaces at the same time. Through the RGB-I/F, the display operation is in synchronization with VSYNC, HSYNC, and DOTCLK. The RGB interface enables data transmission in high speed with low power consumption by only overwriting the area that is needed to update in the high-speed write mode in combination with window address function. Front and back porches must be set before and after the display period. VSYNC ENABLE(V) Back porch period (BP) Moving picture display area Display period (NL) Front porch period (FP) Note 1) The front porch period continues until the next input of VSYNC signal. HSYNC DOTCLK ENABLE(H) PD17-0 Note 2) The DOTCLK signal must be supplied consecutively. VSYNC: Frame synchronization signal HSYNC: Line synchronization signal DOTCLK: DOT clock ENABLE: Data enable signal PD17-0: RGB(6:6:6)display data Back porch period (BP): Front porch period (FP): Display Period The numbers of raster-rows for 1 frame 14HBP2H 14HFP2H FP + BP = 16H NL320H FP+NL+BP Rev.0.5, July.31.2003, page 139 of 196 HD66781 Preliminary In the RGB interface mode, VYSNC, HSYNC and DOTCLK must be supplied more than to achieve the resolution on the liquid crystal panels. Polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals The polarities of VSYNC, HSYNC, ENABLE, DOTCLK signals are changeable by instruction settings (DPL, EPL, HSPL, and VSPL) to conform to the system. RGB interface timing Timing chart of signals in 16/18-bit RGB interface mode 1 frame Back porch period VSYNC Front porch period HSYNC DOTCLK ENABLE PD17-0 1H or more VSYNC 1H HLW HSYNC 1CLK 1 clock DOTCLK DTST ENABLE 1CLK PD17-0 Valid data Note 1) VLW: VSYNC "Low" period HLW: HSYNC "Low" period DTST: Setup time for data transfer Note 2) Write data in the high speed write mode (HWM = 1) in the RGB I/F mode. Rev.0.5, July.31.2003, page 140 of 196 HD66781 Timing chart of signals in 6-bit RGB interface mode 1 frame Back porch period Front porch period Preliminary VSYNC HSYNC DOTCLK ENABLE PD17-0 1H or more VSYNC 1H HLW 3CLK HSYNC 1CLK DOTCLK DTST 1CLK ENABLE RGBRGBRGBRGBRGBRGBRGB PD17-0 Valid data Note 1) VLW: VSYNC "Low" period HLW: HSYNC "Low" period DTST: Setup time for data transfer Note 2) Write data in the high speed write mode (HWM = 1) in the RGB I/F mode. Note 3) VSYNC, HSYNC, EVABLE, DOTCLK, and PD17-0 must be transmitted by 3 clocks. Rev.0.5, July.31.2003, page 141 of 196 HD66781 Moving picture display in RGB Interface Preliminary The HD66781 incorporates the RGB interface to display moving pictures and RAM to store display data, which provides the following merits in displaying moving pictures. * * * * * The window address function enables the transfer of only data for the moving picture area. The high-speed write modes enables high-speed access to RAM with low power consumption Only transfer data that are written over the moving picture area. Reduced transmission contributes to the reduction of power consumption of the entire system. In combination with the system interface, the still picture area, such as an icon, can be updated while displaying moving pictures. RAM access through the system interface in RGB-I/F mode RAM is accessible through the system interface in the RGB-I/F mode. In the RGB interface mode, data are being written to RAM in synchronization with the DOTCLK input while the ENABLE is "Low". When writing data to RAM through the system interface, it is necessary to set ENABLE to "High" to stop data write through the RGB-I/F. Setting RM = 0 allows RAM access through the system interface. When reverting to the RGB interface mode, wait a write/read bus cycle. Then, set RM = 1 and the index to R202h to start RAM access though the RGB-I/F. When RAM write through the RGB and system interfaces conflicts, it is not guaranteed that the data are properly written to RAM. The following is an example of moving picture display through the RGB-I/F and updating still picture area through the system interface. Screen update VSYNC Screen update ENABLE DOTCLK PD17-0 Note 4) System interface Data update in the area other than moving picture area Note 4) In dex R202 Moving picture area Update Index R202 Address Address Set Set RM= 1 Index R202 Moving picture area Update Still picture area update Not e 1) An address set is made every falling edge of VSYNC in the RGB interface mode. N ot e 2) An address set and an index set (R202h) must be made before RAM access through the RGB interface. N ot e 3) Write data in the high-speed write mode (HWM = 1) in the RGB interface mode. Note 4) When transferring to a system interface mode, wait at least 1 write cycle (tcycw) after writing through the RGB interface. 6/2 00:00 6/25 00:00 6/2 00:00 6/25 00:00 Moving picture area Moving picture area Updating still picture area during moving picture display Rev.0.5, July.31.2003, page 142 of 196 HD66781 6-bit RGB interface Preliminary The 6-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 6-bit RGB data bus (PD17-12) according to the data enable signal (ENABLE). Unused pins (PD11 to 0) must be fixed to either IOVcc or GND level. The instructions are set only through the system interface. VSYNC HSYNC LC DC/M PU 6 12 DOTCLK HD 66781 ENABLE PD17-12 PD11-0 First transmission input Second transmission Third transmission PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 GRAM Write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1 pixel 262,144 colors with 6-bit interfacs Example of 6-Bit RGB Interface and data format Rev.0.5, July.31.2003, page 143 of 196 HD66781 Transfer synchronization function for a 6-bit bus interface Preliminary The HD66781 incorporates a transmission counter to count the first, second, third data transmissions in 6bit RBG interface mode. The transmission counter is always reset to the first transmission on the falling edge of the VSYNC. When a discrepancy occurs in the transmission of first, second and third data, the counter is reset to the first data transmission at the start of each frame (the falling edge of VSYNC) and the data transmission restarts in the correct order from the next frame. In case of displaying moving pictures, which requires consecutive data transfer, this function minimizes the effect from the discrepancy in the data transmission and facilitates to return to the normal display. VSYNC ENABLE DOTCLK PD17-0 2nd Transmission Transfer synchronization 1st Transmission 2nd Transmission 3rd 1st TransTransmission mission 2nd Transmission 3rd Transmission 6-bit Transfer Synchronization Rev.0.5, July.31.2003, page 144 of 196 HD66781 16-bit RGB interface Preliminary The 16-bit RGB interface is selected by setting RIM1-0 bits to 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through16-bit RGB data bus (PD17-13, 11-1) according to the data enable signal (ENABLE). The instructions are set only through the system interface. VSYNC HSYNC LCDC/MPU DOTCLK HD66781 ENABLE PD17-13,11-1 16 2 PD12,0 input PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel 65,536 colors with 16-bit interface input PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 GRAM wr e data R5 R4 R3 R2 R1 2 G5 G4 G3 G2 G1 1 B5 B4 B3 B2 B1 0 1 pixel 8,192 colors with 16-bit interface input PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 GRAM write data 2 1 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1 1 pixel 8,192 colors with 16-bit interface Example of 16-Bit RGB Interface and data format Rev.0.5, July.31.2003, page 145 of 196 HD66781 18-bit RGB interface Preliminary The 18-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 18-bit RGB data bus (PD17-0) according to the data enable signal (ENABLE). The instructions are set only through the system interface. VSYNC HSYNC LCDC/MPU DOTCLK HD66781 ENABLE PD17-0 18 input PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 GRAM write data OSD data ODF=0 OSD data ODF=1 R5 R5 2 R4 R4 1 R3 R3 0 R2 R2 R5 R1 R1 R4 R0 2 R3 G5 G5 R2 G4 G4 R1 G3 G3 G5 G2 G2 G4 G1 G1 G3 G0 1 G2 B5 B5 G1 B4 B4 B5 B3 B3 B4 B2 B2 B3 B1 B1 B2 B0 0 B1 1pixel 262,144 colors with 18-bit RGB interface Example of 18-Bit RGB Interface and data format Rev.0.5, July.31.2003, page 146 of 196 HD66781 Notes to the external display interface 1. Preliminary While an external display interface is selected, the following functions are not available. Table 66 Function Partial display Scroll function Interlaced drive External Display Interface Not available Not available Not available Internal Display Operation Available Available Available 2. 3. 4. 5. 6. 7. 8. 9. The VSYNC, HSYNC, and DOTCLK signals must be supplied through the display operation through the RGB-I/F. When making settings for gate driver/LTPS panel controlling signal in the RGB-I/F modes, the reference clock is DOTCLK, not the internal operation clocks. In the 6-bit RGB-I/F mode, the RGB (pixels) data are transmitted by three clocks. In the 6-bit RGB-I/F mode, the interface signals, VSYNC, HSYNC, DOTCL, ENABLE, and PD17-0, should be set by RGB (pixels) unit in convenience for the transmitting RGB pixels. The transitions between the internal operation mode and external display interface should be made according to the mode switching sequence below. In the RGB-I/F mode, the front porch period continues after displaying one frame data until the next VSYNC signal input. In the RGB-I/F mode, the data must be written in the high-speed write mode (HWM = 1). In the RGB-I/F mode, the address is set every frame on the falling edge of VSYNC. From Internal clock operation to RGB I/F (1) Internal clock operation From RGB I/F (1) to Internal clock operation RGB I/F operation Display operation in synchronization with VSYNC, HSYNC, DOTCLK The settings in DM1-0, RM become valid after displaying one frame. HWM = 1, AM = 0 Set Address RGB I/F Setting (DM1-0=01, RM=1) Index resister setting (R202h) Display operation in synchronization with the internal clock Internal clock mode setting (DM1-0 = 00, RM=0) Wait more than 1 frame Internal clock operation Display operation in synchronization with the internal clock The settings in DM1-0, RM become valid after displaying one frame. Wait more than 1 frame RGB I/F Write RAM data RGB interface operation Note: RGB interface signals must be supplied for at least one frame when switching to the internal clock operation. Display operation in synchronization with VSYNC, HSYNC, DOTCLK Note: RGB interface signals must be supplied before setting DM1-0, RM when switching to the RGB I/F mode. Rev.0.5, July.31.2003, page 147 of 196 HD66781 Preliminary Display Synchroniaing Data Transfer The HD66781 outputs BST signal that indicates the start of vertical retrace line period for flicker-free screen update. The BST signal is used as trigger to start internal GRAM write so that data transfer is synchronized with display scan. BST LCDC/MPU CS* RS WR* DB17-10,8-1 HD66781 16 Display synchronizing data transfer: Interface example By writing data to RAM through the system interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it enables moving picture display through an conventional interface and flicker-free screen update. All display data are stored in RAM. Therefore, it only requires transfer of the data that is written over to update the screen, thereby minimizing the numbers of data transfers while displaying moving picture. The use of high-speed write mode (HWM = 1) with VSYNC interface enables RAM access in high speed with low power consumption. BST System interface RAM data Write Display execution with internal clock Moving picture data transmission through VSYNC interface Note 1) Data must be written to RAM in the high-speed write mode (HWM = 1) in VSYNC interface mode. Rev.0.5, July.31.2003, page 148 of 196 HD66781 Preliminary The display synchronizing data transfer mode has limits on the minimum speed for RAM write through the system interface and the frequency of the internal clock. It requires RAM write speed more than the calculated result from the following formula. Internal clock frequency (fosc) [Hz] = Frame frequency x (Display raster-row (NL) + Front porch (FP) +Back porch (BP)) x 16 clocks x Fluctuation RAM writing speed (min.) [Hz] > 320x Display lines (NL)/{[(Front porch (FP)+Back porch (BP)+Display lines (NL) - margin) x 16 clocks] /fosc} When RAM write does not start immediately after the rising edge of BST, the period from the rising edge of BST to the start of RAM write must also be taken into consideration. An example of calculations for the internal clock frequency and RAM write speed in the display synchronizing data transfer mode is as follows. * * * * Calculation Example: moving picture display in VSYNC I/F Panel size 240 RGB x 320 raster-rows (NL0 = 6'27) Total number of raster-rows(NL) 320 raster-rows Back, Front porches 14, 2, raster-rows (BP = 4'hE, FP = 4'h2) * Frame frequency 60Hz Internal clock frequency (fosc) Hz = 60 Hz x (320 + 2 + 14) raster-rows x 16 clocks x 1.1 / 0.9 = 394 [kHz] When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. The allowance for this fluctuation is 10 % from the center value, and the range of the frequency must be within the BST signal cycle. As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room temperature into account. Other possible causes of fluctuations, such as variation in the external resistors or the voltage change are not considered in the above calculation. It is necessary to make a setting with enough margins to include the allowances for these factors. Minimum RAM writing speed [Hz] > 240 x 320 / {((2+14 + 320 - 2) raster-rows x 16 clocks) / 394 kHz} = 5.66 [MHz] In this case, RAM write is performed on the rising edge of BST. When the data for one frame are written to RAM completely, there must be 2 raster-rows or more of a margin before the display raster-rows. According to the above calculation results, writing data to RAM on the rising of BST at the speed of 5.66 MHz or more, the data for the entire screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to moving picture update can be avoided even if displaying a moving picture. Rev.0.5, July.31.2003, page 149 of 196 HD66781 BST RAM write Front porch (2 lines) Back porch (14 lines) Display operation [lines] 320 RAM write (10MHz)76,800 times Preliminary R-C oscillation 10% line processing RAM write 5.66MHz Display operation Panel Moving picture Display (320 lines) 0 FP+BP=16H BST 7.68 13.4 13.5 [ms] 16.67 (60Hz) Front porch (2 lines) Back porch (14 lines) Minimum RAM write speed and internal clock frequency in VSYNC interface Notes to the display synchronizing GRAM data transfer mode 1. The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations such as internal oscillators and so on should be taken into consideration. It is necessary to make a setting for RAM write speed with enough margins. In the display synchronizing GRAM data transfer mode, write display data to RAM in the high speed write mode (HWM = 1) 2. Rev.0.5, July.31.2003, page 150 of 196 HD66781 Preliminary Timing interfacing with LCD panel signals The relationship between RGB I/F signals and LCD panel signals during internal operation is as follows. Timing interfacing with liquid crystal panel signals in RGB interface mode 1 frame Back porch period Front porch period VSYNC HSYNC DOTCLK ENABLE 1H PD17-0 1 2 3 4 5 6 315 316 317 318 319 320 5DOTCLK 5DOTCLK FLM CL1 DPT G1 G2 Gn Gn+1 G320 SDT S1~720 1 2 3 4 n-1 n n+1 n+2 317 318 319 320 EQ (EQ) M (VCOM) (BST) Note 1) This figure is the example when DIVE[1:0] = 2'h2 Rev.0.5, July.31.2003, page 151 of 196 HD66781 Timing interfacing with liquid crystal panel signals in internal clock operation mode 1 frame 1H Front porch period + Back porch period Preliminary (CL1) DPT G1 G2 Gn Gn+1 G320 SDT S1~720 1 2 3 4 n-1 n n+1 n+2 317 318 319 320 EQ (EQ) M (VCOM) (BST) Rev.0.5, July.31.2003, page 152 of 196 HD66781 Preliminary High-Speed Burst RAM Write Function The HD66781 incorporates high-speed burst RAM-write function, which writes data to RAM about half the time required for the normal RAM write. This function is especially useful for applications, which require high-speed display data rewrite, such as colored moving picture display and so on. In the high-speed RAM-write mode (HWM=1), data to write to RAM is temporarily stored to the internal register of HD66781 and then written to RAM by horizontal line in the area specified by the window address. Since the data stored in the register are written to RAM at once, it is possible to write next data to the internal register while data are being written from the internal register to RAM. This reduces the frequency of RAM access to minimum and enables consecutive high-speed access to the internal RAM with low power consumption, which is required for moving picture display. Microcomputer Latch circuit 18 Address counter AC 17 Register 1 Register 2 Register n 18 x n 18'h0-0000 18'h0-0001 18'h0-0003 GRAM High-speed consecutive access to RAM, operational flow CS input 1 WR input 2 ... n 1 2 ... n 1 2 ... n RAM data DB17-0 input index (R202) (1) (2) ... (n) (1) (2) ... (n) (1) (2) ... (n) index (R202) RAM write execution time RAM write execution time RAM write execution time x 2 Note) RAM write data (18 x n bits) RAM data (1) - (n) 18'h00000 - 18'h0000n RAM data (n+1) - (2n) 18'h00100 - 18'h0010n RAM data (2n+1) - (3n) 18'h00200 - 18'h0020n RAM address (AC17-0) High-speed consecutive access to RAM (HWM = "1") Note 1) When making a transition from the high-speed RAM write to the index write, wait at least 2 bus cycle time (tcycw) in the normal write mode after RAM write before executing next instructions. Rev.0.5, July.31.2003, page 153 of 196 HD66781 CS in put 1 WR in put 2 3 4 5 6 7 8 Preliminary DB 17-0 in put index R202 RAM data upper (1) RAM data lower (1) RAM data upper (n) RAM data lower (n) RAM data upper (1) RAM data lower (1) RAM data upper (n) RAM data lower (n) RAM wri t e execut ion t ime RAM wri t e execut ion t ime RAM wri t e dat a (18 x n bit s) RAM data (1) - (n) RAM data (n+1) - (2n) RAM ad dr ess (AC16-0) 18'h00000 - 18'h0000n 18'h00100 - 18'h0010n High-speed consecutive access to RAM (9-bit interface) Note 1) The high-speed RAM write mode (HWM=1) writes data to RAM by n words. In the 9-bit interface mode, data are written to RAM 2xn times per line. Notes to the high-speed RAM write mode 1. RAM write is executed by line. If write operation is terminated before it reaches the end of horizontal line of the window-address area, it is not guaranteed that data are properly written on that line. The index register for the RAM data write (202H), if selected, executes the first data write operation. This setting does not allow RAM data read. HWM must be set to 0 during RAM read. The high-speed RAM write mode is not compatible with the normal RAM write mode. Whenever switching to the other mode, it is necessary to set the address before starting RAM write. 2. 3. Table 67 Normal RAM Write (HWM=0) BGR function Write mask function RAM address set RAM read RAM write Window address External display interface AM Available Available Set by words Set by words Set by words Set by words (minimum range: 1 word x 1 line) Available AM = 1/0 High-Speed RAM Write (HWM=1) Available Available Set by words Not available Set by lines Set by words (minimum range: 8 word x 1 line) Available AM = 0 Rev.0.5, July.31.2003, page 154 of 196 HD66781 High-Speed RAM Write with Window Address Function Preliminary Specifying a window-address range (minimum range: 8 words x 1 word) enables consecutive high-speed RAM data write in an arbitrary rectangular area on RAM. In the high-speed write mode, data must be written to RAM by horizontal lines. If RAM write is terminated in the middle of the line, there is no guarantee that data are properly written on that line. The following figure illustrates an example of high-speed RAM write in the window-address range on RAM. By setting the window address specifying bits (HSA = 8'h10, HEA = 8'h2F, VSA = 9'h020, VEA = 9'h05F), data are written consecutively in high speed in the window-address range specified by these bits. Write in the horizontal direction AM = 0, I D0 = 1 Wi ndow addr ess-r ange set t ing HA S = 8'h12, HE A = 8'hA8 VSA = 9'h020, VEA = 9'h05F H i gh-speed RAM w r i t e mode setting HW M = 1 00000h GRAM addr ess map 18'h02012 Wi ndow addr ess-r ange (overwritten area) Addr ess set AD = 18'h02010* 18'h05BA7 10F83h RAM w r i t e x 150 x 60 times Wi ndow addr ess-r ange set t ing HA S = 8'h10, HE A = 8'h2F VSA = 9'h020, VEA = 9'h05F * Note: Make an address set within the window address Rev.0.5, July.31.2003, page 155 of 196 HD66781 Preliminary Window Address Function The window address function writes data consecutively to the on-chip GRAM within the rectangular window-address range specified by the horizontal address registers (start: HSA7-0, end: HEA 7-0) and the vertical address registers (start: VSA7-0, end: VEA7-0). The address transition direction is determined by AM bit (either increment or decrement). This allows writing data, including picture data, consecutively without taking the data wrap position into consideration. The window-address range must be specified within the GRAM address area. An address set must be made within the window-address range. [Conditions on setting window-address range] (horizontal direction) 8'h00 HSA HEA 8'hEF (vertical direction) 9'h000 VSA VEA 9'h19F [Conditions on making an address set within the window-address range] (RAM address) HSA AD7-0 HEA VSA AD16-8 VEA GRAM address map 18'h00000 18'h000EF Window address area 18'h02010 18'h02110 18'h0202F 18'h0212F 18'h05F10 18'h05F2F 18'h19F00 18'h19FEF Window address range setting HSA= 8'h10, HEA = 8'h2F I/D = 2'h3(increment) VSA = 9'h020,VEA = 9'h05F AM = 1'h0(Horizontal write) Address transition direction in specified window-address range Rev.0.5, July.31.2003, page 156 of 196 HD66781 Preliminary -Correction Function The HD66781 incorporates -correction function to simultaneously display 262,144 colors, by which 8level grayscale is determined by the gradient-adjustment and fine-adjustment registers. The HD66781 incorporates gradient-adjustment and fine-adjustment registers for both positive and negative polarities and allows selecting either positive or negative polarity according to the characteristics of a liquid crystal panel. MSB Display data GRAM LSB B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 + polar register PKP0[2:0] PKP1[2:0] PKP2[2:0] PKP3[2:0] PKP4[2:0] PKP5[2:0] PRP0[2:0] PRP1[2:0] VRP0[3:0] VRP1[4:0] - polar register PKN0[2:0] PKN1[2:0] PKN2[2:0] PKN3[2:0] PKN4[2:0] PKN5[2:0] PRN0[2:0] PRN1[2:0] VRN0[3:0] VRN1[4:0] V0 V1 64 6 64 gray-scale control 6 64 gray-scale control 6 64 gray-scale control Gray-scale amp 8 LCD driver LCD driver LCD driver RGB LCD LCD Grayscale control Rev.0.5, July.31.2003, page 157 of 196 HD66781 Grayscale Amplifier Configuration The following figure illustrates the configuration of grayscale amplifier. Preliminary The eight-level grayscales (VIN0-7) are determined by the gradient adjustment and fine adjustment registers. The 8 levels are then divided by the ladder resistors placed between each level into 64 levels (V0-63). Increment adjustment PRP/N0,PRP/N1 PKP/N0 Fine adjustment(6 x 3 bits) PKP/N1 PKP/N2 PKP/N3 PKP/N4 PKP/N5 Amplitude adjustment VRP/N0 VRP/N1 VDH 3 3 3 3 3 3 3 3 4 5 VINP0 /VINN0 V0 VINP1 /VINN1 8 to 1 selector V1 V2 V3 VINP2 /VINN2 8 to 1 selector VINP3 /VINN3 8 to 1 selector VINP4 /VINN4 8 to 1 selector VINP5 /VINN5 8 to 1 selector V8 V9 V20 V21 V43 V44 V55 V56 V57 Gray-scale ope-amp Ladder resistor VINP6 /VINN6 8 to 1 selector V62 VINP7 /VINN7 V63 VGS Grayscale amplifier Rev.0.5, July.31.2003, page 158 of 196 HD66781 VDH VRP0 0 ~ 15R Preliminary VRP0[3:0] KVP0 VRN0 1 ~ 15R VINP0 PKP0 [2:0] 5R RN0 VRN0[3:0] KVP0 VINN0 PKN0[2:0] 5R RP0 KVP1 RP1 RP2 RP3 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 8 to 1 SEL KVN1 RN1 RN2 VINP1 RN3 4R RN4 RN5 RN6 RN7 PKP1 [2:0] VRHN 0~28R KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 8 to 1 SEL VINN1 4R RP4 RP5 RP6 RP7 VRHP 0~28R PRP0[2:0] KVP9 RP8 RP9 RP10 1R RP11 RP12 RP13 RP14 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 8 to 1 SEL PRN0[2:0] KVN9 RN8 RN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 8 to 1 SEL PKN1[2:0] VINP2 RN10 1R RN11 RN12 RN13 RN14 VINN2 5R RP15 KVP17 RP16 RP17 RP18 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 8 to 1 SEL PKP2 [2:0] 5R RN15 KVN17 RN16 RN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 8 to 1 SEL PKN2[2:0] 1R RP19 RP20 RP21 RP22 VINP3 RN18 1R RN19 RN20 RN21 RN22 VINN3 16R RP23 KVP25 RP24 RP25 RP26 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 8 to 1 SEL PKP3 [2:0] 16R RN23 KVN25 RN24 RN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 8 to 1 SEL PKN3[2:0] 1R RP27 RP28 RP29 RP30 VINP4 RN26 1R RN27 RN28 RN29 RN30 VINN4 5R RP31 KVP33 RP32 RP33 RP34 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 8 to 1 SEL PKP4 [2:0] 5R RP31 KVN33 RN32 RN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 8 to 1 SEL PKN4[2:0] 1R RP35 RP36 RP37 RP38 VINP5 RN34 1R RN35 RN36 RN37 RN38 VRLN 0~28R VINN5 VRLP 0~28R PRP1[2:0] KVP41 RP39 RP40 RP41 4R RP42 RP43 RP44 RP45 5R RP46 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 VRP[4:0] 8R RP47 8 to 1 SEL PKP5 [2:0] PRN1[2:0] KVN41 RN39 RN40 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 VRN[4:0] 8R RN47 8 to 1 SEL PKN5[2:0] VINP6 RN41 4R RN42 RN43 RN44 RN45 5R RN46 VINN6 VRP1 0~31R VGS VINP7 VINN7 VRN1 0~31R Ladder Resistors and 8 to 1 Selectors Rev.0.5, July.31.2003, page 159 of 196 HD66781 -Correction Registers Preliminary The -adjustment register is a group of registers to set an appropriate grayscale voltage for the characteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient, amplitude, and reference value and fine-tuning in relation to grayscale number and grayscale voltage characteristics. Each register group can make an independent setting for the positive/negative polarity. The reference value and RGB are common to both polarities. Gray-scale voltage Gray-scale number Gray-scale voltage Gray-scale voltage Gray-scale number Gray-scale number Gradient adjustment Amplitude adjustment Fine adjustment Gradient, Amplitude, Fine Adjustments 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient around the middle of the grayscale number and voltage characteristics without changing a dynamic range. To adjust a gradient, the values of the variable resistors (VRHP (N)/VRLP (N)) in the ladder resistor block for grayscale voltage generation are controlled. The registers incorporate separate registers for positive and negative polarities to be compatible with asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. To adjust the amplitude, the values of the variable resistors (VRP(N)1/0) in the upper and lower parts of the ladder resistor block for grayscale voltage generation are adjusted. Same with the gradient registers, the amplitude adjustment registers also incorporate separate registers for positive and negative polarities. 3. Fine adjustment registers The fine adjustment register is to fine-adjust the grayscale voltage level. To fine-adjust the grayscale voltage level, 8-to-1 selectors control each level of 8-level reference voltages generated from the ladder registers. Same with the other registers, the fine adjustment registers also incorporate separate registers for positive and negative polarities. Rev.0.5, July.31.2003, page 160 of 196 HD66781 Table 68 Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Preliminary List of output signals Positive Polarity PRP0 [2:0] PRP1 [2:0] VRP0 [3:0] VRP1 [4:0] PKP0 [2:0] PKP1 [2:0] PKP2 [2:0] PKP3 [2:0] PKP4 [2:0] PKP5 [2:0] Negative Polarity PRN0 [2:0] PRN1 [2:0] VRN0 [3:0] VRN1 [4:0] PKN0 [2:0] PKN1 [2:0] PKN2 [2:0] PKN3 [2:0] PKN4 [2:0] PKN5 [2:0] Description Variable resistor VRHP (N) Variable resistor VRLP (N) Variable resistor VRP (N) 0 Variable resistor VRP (N) 1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62) Rev.0.5, July.31.2003, page 161 of 196 HD66781 Ladder resistors and 8 to 1 selector Block configuration Preliminary The block configuration of page 159 consists of two ladder resistors including variable resistors, and 8 to 1 selectors, which select the voltage generated by the ladder resistors, to output the reference voltage for the grayscale voltage. The -correction registers control the variable resistors and the 8 to 1 selectors. Pins that are connected to a variable resistor are also provided to compensate the variation among the panels. Variable resistors There are three kinds of variable resistors for the gradient adjustment (VRHP(N)/VRLP(N)), the amplitude adjustment (VRP(N)), and the reference adjustment (VDR). The resistance is determined by the gradient adjustment and amplitude adjustment registers as is shown below. Table 69 Gradient adjustment Register PRP(N)0/1[2:0] Resistance VRHP(N) VRLP(N) Amplitude adjustment Register VRP(N)0[3:0] Resistance VRP(N)0 Reference adjustment Register VRP(N)1[4:0] Resistance VRP(N)1 000 001 010 011 100 101 110 111 0R 4R 8R 12R 16R 20R 24R 28R 0000 0001 0010 : : 1101 1110 1111 0R 1R 2R : : 13R 14R 15R 00000 00001 00010 : : 11101 11110 11111 0R 1R 2R : : 29R 30R 31R 8 to 1 selector The 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment registers, and output as a reference voltage of either one of the following VIN1 ~ VIN 6. The relationship between the fine adjustment register and the selected voltage is as follows Table 70 Contents of Register PKP(N) 0/1 [2:0] Selected Voltage 000 001 010 011 100 101 110 111 VINP(N)1 KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8 VINP(N)2 KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16 VINP(N)3 KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 VINP(N)4 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48 Rev.0.5, July.31.2003, page 162 of 196 HD66781 The gray scale levels (V0-V63) are calculated according to the following formulas. Formulas for calculating voltage (Positive polarity) (1) Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- V*VxP0/SUMRP V*(VxRP0+5R)/SUMRP V*(VxRP0+9R)/SUMRP V*(VxRP0+13R)/SUMRP V*(VxRP0+17R)/SUMRP V*(VxRP0+21R)/SUMRP V*(VxRP0+25R)/SUMRP V*(VxRP0+29R)/SUMRP V*(VxRP0+33R)/SUMRP V**i VxRP0+33R+VRHP*j /SUMRP V**i VxRP0+34R+VRHP*j /SUMRP V**i VxRP0+35R+VRHP*j /SUMRP V**i VxRP0+36R+VRHP*j /SUMRP V**i VxRP0+37R+VRHP*j /SUMRP V**i VxRP0+38R+VRHP*j /SUMRP V**i VxRP0+39R+VRHP*j /SUMRP V**i VxRP0+40R+VRHP*j /SUMRP V**i VxRP0+45R+VRHP*j /SUMRP V**i VxRP0+46R+VRHP*j /SUMRP V**i VxRP0+47R+VRHP*j /SUMRP V**i VxRP0+48R+VRHP*j /SUMRP V**i VxRP0+49R+VRHP*j /SUMRP V**i VxRP0+50R+VRHP*j /SUMRP V**i VxRP0+51R+VRHP*j /SUMRP V**i VxRP0+52R+VRHP*j /SUMRP V**i VxRP0+68R+VRHP*j /SUMRP V**i VxRP0+69R+VRHP*j /SUMRP V**i VxRP0+70R+VRHP*j /SUMRP V**i VxRP0+71R+VRHP*j /SUMRP V**i VxRP0+72R+VRHP*j /SUMRP V**i VxRP0+73R+VRHP*j /SUMRP V**i VxRP0+74R+VRHP*j /SUMRP V**i VxRP0+75R+VRHP*j /SUMRP V**i VxRP0+80R+VRHP*j /SUMRP V**i VxRP0+81R+VRHP*j /SUMRP V**i VxRP0+82R+VRHP*j /SUMRP V**i VxRP0+83R+VRHP*j /SUMRP V**i VxRP0+84R+VRHP*j /SUMRP V**i VxRP0+85R+VRHP*j /SUMRP V**i VxRP0+86R+VRHP*j /SUMRP V**i VxRP0+87R+VRHP*j /SUMRP V**i VxRP0+87R+VRHP+VRLP*j /SUMRP V**i VxRP0+91R+VRHP+VRLP*j /SUMRP V**i VxRP0+95R+VRHP+VRLP*j /SUMRP V**i VxRP0+99R+VRHP+VRLP*j /SUMRP V**i VxRP0+103R+VRHP+VRLP*j /SUMRP V**i VxRP0+107R+VRHP+VRLP*j /SUMRP V**i VxRP0+111R+VRHP+VRLP*j /SUMRP V**i VxRP0+115R+VRHP+VRLP*j /SUMRP V**i VxRP0+120R+VRHP+VRLP*j /SUMRP Formula Preliminary Fine-adjustment registers *| PKP0[2:0]="000" PKP0[2:0]="001" PKP0[2:0]="010" PKP0[2:0]="011" PKP0[2:0]="100" PKP0[2:0]="101" PKP0[2:0]="110" PKP0[2:0]="111" PKP1[2:0]="000" PKP1[2:0]="001" PKP1[2:0]="010" PKP1[2:0]="011" PKP1[2:0]="100" PKP1[2:0]="101" PKP1[2:0]="110" PKP1[2:0]="111" PKP2[2:0]="000" PKP2[2:0]="001" PKP2[2:0]="010" PKP2[2:0]="011" PKP2[2:0]="100" PKP2[2:0]="101" PKP2[2:0]="110" PKP2[2:0]="111" PKP3[2:0]="000" PKP3[2:0]="001" PKP3[2:0]="010" PKP3[2:0]="011" PKP3[2:0]="100" PKP3[2:0]="101" PKP3[2:0]="110" PKP3[2:0]="111" PKP4[2:0]="000" PKP4[2:0]="001" PKP4[2:0]="010" PKP4[2:0]="011" PKP4[2:0]="100" PKP4[2:0]="101" PKP4[2:0]="110" PKP4[2:0]="111" PKP4[2:0]="000" PKP5[2:0]="001" PKP5[2:0]="010" PKP5[2:0]="011" PKP5[2:0]="100" PKP5[2:0]="101" PKP5[2:0]="110" PKP5[2:0]="111" *| Reference voltage VINP0 VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 VINP7 Note 1) Sum of ladder resistors with positive polarities = 128R+VRHP+VRLP+VRP0+VRP1 Note 2) Sum of ladder resistors with negative polarities = 128R+VRHN+VRLN+VRN0+VRN1 Note 3) V :Electric potential difference between VDH and VGS Rev.0.5, July.31.2003, page 163 of 196 HD66781 Formulas for calculating voltage (Positive polarity) (2) Preliminary Grayscale Grayscale Formula Formula voltage voltage V0 VINP0 V32 V43+(V20-V43)*(11/23) V1 VINP1 V33 V43+(V20-V43)*(10/23) V2 V8+(V1-V8)*(30/48) V34 V43+(V20-V43)*(9/23) V3 V8+(V1-V8)*(23/48) V35 V43+(V20-V43)*(8/23) V4 V8+(V1-V8)*(16/48) V36 V43+(V20-V43)*(7/23) V5 V8+(V1-V8)*(12/48) V37 V43+(V20-V43)*(6/23) V6 V8+(V1-V8)*(8/48) V38 V43+(V20-V43)*(5/23) V7 V8+(V1-V8)*(4/48) V39 V43+(V20-V43)*(4/23) V8 VINP2 V40 V43+(V20-V43)*(3/23) V9 V20+(V8-V20)*(22/24) V41 V43+(V20-V43)*(2/23) V10 V20+(V8-V20)*(20/24) V42 V43+(V20-V43)*(1/23) V11 V20+(V8-V20)*(18/24) V43 VINP4 V12 V20+(V8-V20)*(16/24) V44 V55+(V43-V55)*(22/24) V13 V20+(V8-V20)*(14/24) V45 V55+(V43-V55)*(20/24) V14 V20+(V8-V20)*(12/24) V46 V55+(V43-V55)*(18/24) V15 V20+(V8-V20)*(10/24) V47 V55+(V43-V55)*(16/24) V16 V20+(V8-V20)*(8/24) V48 V55+(V43-V55)*(14/24) V17 V20+(V8-V20)*(6/24) V49 V55+(V43-V55)*(12/24) V18 V20+(V8-V20)*(4/24) V50 V55+(V43-V55)*(10/24) V19 V20+(V8-V20)*(2/24) V51 V55+(V43-V55)*(8/24) V20 VINP3 V52 V55+(V43-V55)*(6/24) V21 V43+(V20-V43)*(22/23) V53 V55+(V43-V55)*(4/24) V22 V43+(V20-V43)*(21/23) V54 V55+(V43-V55)*(2/24) V23 V43+(V20-V43)*(20/23) V55 VINP5 V24 V43+(V20-V43)*(19/23) V56 V62+(V55-V62)*(44/48) V25 V43+(V20-V43)*(18/23) V57 V62+(V55-V62)*(40/48) V26 V43+(V20-V43)*(17/23) V58 V62+(V55-V62)*(36/48) V27 V43+(V20-V43)*(16/23) V59 V62+(V55-V62)*(32/48) V28 V43+(V20-V43)*(15/23) V60 V62+(V55-V62)*(25/48) V29 V43+(V20-V43)*(14/23) V61 V62+(V55-V62)*(18/48) V30 V43+(V20-V43)*(13/23) V62 VINP6 V31 V43+(V20-V43)*(12/23) V63 VINP7 Note 1) Make sure DDVDH - V0 > 0.5V, DDVDH - V4 > 1.1V, V55-GND > 1.1V Rev.0.5, July.31.2003, page 164 of 196 HD66781 Formulas for calculating voltage (Negative polarity) (1) Pins KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- VDH- V*VxRN0/SUMRN V*(VxRN0+5R)/SUMRN V*(VxRN0+9R)/SUMRN V*(VxRN0+13R)/SUMRN V*(VxRN0+17R)/SUMRN V*(VxRN0+21R)/SUMRN V*(VxRN0+25R)/SUMRN V*(VxRN0+29R)/SUMRN V*(VxRN0+33R)/SUMRN V**i VxRN0+33R+VRHN*j /SUMRN V**i VxRN0+34R+VRHN*j /SUMRN V**i VxRN0+35R+VRHN*j /SUMRN V**i VxRN0+36R+VRHN*j /SUMRN V**i VxRN0+37R+VRHN*j /SUMRN V**i VxRN0+38R+VRHN*j /SUMRN V**i VxRN0+39R+VRHN*j /SUMRN V**i VxRN0+40R+VRHN*j /SUMRN V**i VxRN0+45R+VRHN*j /SUMRN V**i VxRN0+46R+VRHN*j /SUMRN V**i VxRN0+47R+VRHN*j /SUMRN V**i VxRN0+48R+VRHN*j /SUMRN V**i VxRN0+49R+VRHN*j /SUMRN V**i VxRN0+50R+VRHN*j /SUMRN V**i VxRN0+51R+VRHN*j /SUMRN V**i VxRN0+52R+VRHN*j /SUMRN V**i VxRN0+68R+VRHN*j /SUMRN V**i VxRN0+69R+VRHN*j /SUMRN V**i VxRN0+70R+VRHN*j /SUMRN V**i VxRN0+71R+VRHN*j /SUMRN V**i VxRN0+72R+VRHN*j /SUMRN V**i VxRN0+73R+VRHN*j /SUMRN V**i VxRN0+74R+VRHN*j /SUMRN V**i VxRN0+75R+VRHN*j /SUMRN V**i VxRN0+80R+VRHN*j /SUMRN V**i VxRN0+81R+VRHN*j /SUMRN V**i VxRN0+82R+VRHN*j /SUMRN V**i VxRN0+83R+VRHN*j /SUMRN V**i VxRN0+84R+VRHN*j /SUMRN V**i VxRN0+85R+VRHN*j /SUMRN V**i VxRN0+86R+VRHN*j /SUMRN V**i VxRN0+87R+VRHN*j /SUMRN V**i VxRN0+87R+VRHN+VRLN*j /SUMRN V**i VxRN0+91R+VRHN+VRLN*j /SUMRN V**i VxRN0+95R+VRHN+VRLN*j /SUMRN V**i VxRN0+99R+VRHN+VRLN*j /SUMRN V**i VxRN0+103R+VRHN+VRLN*j /SUMRN V**i VxRN0+107R+VRHN+VRLN*j /SUMRN V**i VxRN0+111R+VRHN+VRLN*j /SUMRN V**i VxRN0+115R+VRHN+VRLN*j /SUMRN V**i VxRN0+120R+VRHN+VRLN*j /SUMRN Formula Preliminary Fine-adjustment registers *| PKN0[2:0]="000" PKN0[2:0]="001" PKN0[2:0]="010" PKN0[2:0]="011" PKN0[2:0]="100" PKN0[2:0]="101" PKN0[2:0]="110" PKN0[2:0]="111" PKN1[2:0]="000" PKN1[2:0]="001" PKN1[2:0]="010" PKN1[2:0]="011" PKN1[2:0]="100" PKN1[2:0]="101" PKN1[2:0]="110" PKN1[2:0]="111" PKN2[2:0]="000" PKN2[2:0]="001" PKN2[2:0]="010" PKN2[2:0]="011" PKN2[2:0]="100" PKN2[2:0]="101" PKN2[2:0]="110" PKN2[2:0]="111" PKN3[2:0]="000" PKN3[2:0]="001" PKN3[2:0]="010" PKN3[2:0]="011" PKN3[2:0]="100" PKN3[2:0]="101" PKN3[2:0]="110" PKN3[2:0]="111" PKN4[2:0]="000" PKN4[2:0]="001" PKN4[2:0]="010" PKN4[2:0]="011" PKN4[2:0]="100" PKN4[2:0]="101" PKN4[2:0]="110" PKN4[2:0]="111" PKN4[2:0]="000" PKN5[2:0]="001" PKN5[2:0]="010" PKN5[2:0]="011" PKN5[2:0]="100" PKN5[2:0]="101" PKN5[2:0]="110" PKN5[2:0]="111" *| Reference voltage VINN0 VINN1 VINN2 VINN3 VINN4 VINN5 VINN6 VINN7 Note 1) Sum of ladder resistors with positive polarities = 128R+VRHP+VRLP+VRP0+VRP1 Note 2) Sum of ladder resistors with negative polarities = 128R+VRHN+VRLN+VRN0+VRN1 Note 3) V :Electric potential difference between VDH and VGS Rev.0.5, July.31.2003, page 165 of 196 HD66781 Formulas for calculating voltage (Negative polarity) (2) Grayscale Grayscale Formula voltage voltage V0 VINN0 V32 V1 VINN1 V33 V2 V8+(V1-V8)*(30/48) V34 V3 V8+(V1-V8)*(23/48) V35 V4 V8+(V1-V8)*(16/48) V36 V5 V8+(V1-V8)*(12/48) V37 V6 V8+(V1-V8)*(8/48) V38 V7 V8+(V1-V8)*(4/48) V39 V8 VINN2 V40 V9 V20+(V8-V20)*(22/24) V41 V10 V20+(V8-V20)*(20/24) V42 V11 V20+(V8-V20)*(18/24) V43 V12 V20+(V8-V20)*(16/24) V44 V13 V20+(V8-V20)*(14/24) V45 V14 V20+(V8-V20)*(12/24) V46 V15 V20+(V8-V20)*(10/24) V47 V16 V20+(V8-V20)*(8/24) V48 V17 V20+(V8-V20)*(6/24) V49 V18 V20+(V8-V20)*(4/24) V50 V19 V20+(V8-V20)*(2/24) V51 V20 VINN3 V52 V21 V43+(V20-V43)*(22/23) V53 V22 V43+(V20-V43)*(21/23) V54 V23 V43+(V20-V43)*(20/23) V55 V24 V43+(V20-V43)*(19/23) V56 V25 V43+(V20-V43)*(18/23) V57 V26 V43+(V20-V43)*(17/23) V58 V27 V43+(V20-V43)*(16/23) V59 V28 V43+(V20-V43)*(15/23) V60 V29 V43+(V20-V43)*(14/23) V61 V30 V43+(V20-V43)*(13/23) V62 V31 V43+(V20-V43)*(12/23) V63 Note 1) Make sure DDVDH - V0 > 0.5V, DDVDH - V4 > 1.1V, V55-GND > 1.1V Preliminary Formula V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINN4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINN5 V62+(V55-V62)*(44/48) V62+(V55-V62)*(40/48) V62+(V55-V62)*(36/48) V62+(V55-V62)*(32/48) V62+(V55-V62)*(25/48) V62+(V55-V62)*(18/48) VINN6 VINN7 Rev.0.5, July.31.2003, page 166 of 196 HD66781 Relationship between RAM data and output level (REV =0) The relationship between the RAM data and the source output level is as follows. Preliminary V0 Negative polarity Output level Positive polarity V63 RAM data (Common characteristics to RGB) 000000 RAM data and the output voltage (REV = 0) Sn Negative polarity Vcom Positive polarity Source output and Vcom Rev.0.5, July.31.2003, page 167 of 196 111111 HD66781 Relationship between RAM data and output level (REV =1) The relationship between the RAM data and the source output level is as follows. V0 Negative polarity Preliminary Output level Positive polarity V63 111111 RAM data (Common characteristics to RGB) RAM data and the output voltage (REV = 1) Sn Negative polarity Vcom Positive polarity Source output and Vcom Rev.0.5, July.31.2003, page 168 of 196 000000 HD66781 Preliminary Low Power Consumption Display Mode Setting COL[1:0] to 2'h1 halts 32 amplifiers among V0 ~ V63 grayscale amplifiers to display with low power consumption. In combination with the FRC mode setting, it is possible to realize display with low power consumption in abundant colors. To make a setting for the low power consumption display, set in accordance to the following table according to the interface in use. The setting must be made in accordance to the setting sequence for low power consumption display mode. Using this mode with short screen refreshing cycle may affect the quality of display. Consider the trade-off between the display quality and power-saving effects before use. Table 71 Interface mode 18 bit, 16 bit x2, 9 bit x2, 8 bit x3, RGB18bit, 6 bit x3 16bit x1, 8 bit x2, SPI FRCON 0 1 0 1 D16B * 0 * 1 Available colors 262,144 250,047 65,536 64,512 Note 1) When the FRC mode is on, do not switch the interface mode settings (M, TRI, D16B registers) Note 2) When the FRC mode is on, 18-bit format data and 16-bit format data are not displayed simultaneously. Table 72 COL[1:0] 2'h0 2'h1 2'h2 2'h3 Amplifiers in operation 64 32 2 Setting disabled Available colors for display FRCON = 0 262,144 colors/65,536 colors 32,768 colors 8 colors Setting disabled FRCON = 1 250,047 colors/64,512 colors Setting disabled Note 1) When COL[1:0] =2'h1 and FRCON = 0, do not write data that correspond to the grayscale levels for which the amplifiers are halted. Rev.0.5, July.31.2003, page 169 of 196 HD66781 Table 73 amplifier V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Preliminary grayscale level amplifiers in operation COL[1:0] 2'h0 2'h1 2'h2 GRAM data RGB 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F 6'h3F 6'h3E 6'h3D 6'h3C 6'h3B 6'h3A 6'h39 6'h38 6'h37 6'h36 6'h35 6'h34 6'h33 6'h32 6'h31 6'h30 6'h2F 6'h2E 6'h2D 6'h2C 6'h2B 6'h2A 6'h29 6'h28 6'h27 6'h26 6'h25 6'h24 6'h23 6'h22 6'h21 6'h20 amplifier V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 COL[1:0] 2'h0 2'h1 2'h2 GRAM data RGB 6'h20 6'h1F 6'h1E 6'h1D 6'h1C 6'h1B 6'h1A 6'h19 6'h18 6'h17 6'h16 6'h15 6'h14 6'h13 6'h12 6'h11 6'h10 6'h0F 6'h0E 6'h0D 6'h0C 6'h0B 6'h0A 6'h09 6'h08 6'h07 6'h06 6'h05 6'h04 6'h03 6'h02 6'h01 6'h00 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F *: amplifier in operation Rev.0.5, July.31.2003, page 170 of 196 HD66781 Preliminary The following table shows the relationship between GRAM data and liquid crystal grayscale level. Table 74 GRAM data and LCD grayscale level (REV = 0) in FRC mode GRAM data RGB Selected grayscale level positive V0 (V0+V2)/2 V2 (V2+V4)/2 V4 (V4+V6)/2 V6 (V6+V8)/2 V8 (V8+V10)/2 V10 (V10+V12)/2 V12 (V12+V14)/2 V14 (V14+V16)/2 V16 (V16+V18)/2 V18 (V18+V20)/2 V20 (V20+V22)/2 V22 (V22+V24)/2 V24 (V24+V26)/2 V26 (V26+V28)/2 V28 (V28+V30)/2 V30 (V30+V33)/2 negative V63 (V61+V63)/2 V61 (V59+V61)/2 V59 (V57+V59)/2 V57 (V55+V57)/2 V55 (V53+V55)/2 V53 (V51+V53)/2 V51 (V49+V51)/2 V49 (V47+V49)/2 V47 (V45+V47)/2 V45 (V43+V45)/2 V43 (V41+V43)/2 V41 (V39+V41)/2 V39 (V37+V39)/2 V37 (V35+V37)/2 V35 (V33+V35)/2 V33 (V30+V33)/2 GRAM data RGB Selected grayscale level positive (V30+V33)/2 V33 (V33+V35)/2 V35 (V35+V37)/2 V37 (V37+V39)/2 V39 (V39+V41)/2 V41 (V41+V43)/2 V43 (V43+V45)/2 V45 (V45+V47)/2 V47 (V47+V49)/2 V49 (V49+V51)/2 V51 (V51+V53)/2 V53 (V53+V55)/2 V55 (V55+V57)/2 V57 (V57+V59)/2 V59 (V59+V61)/2 V61 (V61+V63)/2 V63 negative (V30+V33)/2 V30 (V28+V30)/2 V28 (V26+V28)/2 V26 (V24+V26)/2 V24 (V22+V24)/2 V22 (V20+V22)/2 V20 (V18+V20)/2 V18 (V16+V18)/2 V16 (V14+V16)/2 V14 (V12+V14)/2 V12 (V10+V12)/2 V10 (V8+V10)/2 V8 (V6+V8)/2 V6 (V4+V6)/2 V4 (V2+V4)/2 V2 (V0+V2)/2 V0 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2D 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3D 6'h3E 6'h3F Note 1) This table shows effective grayscale levels by FRC grayscale. Rev.0.5, July.31.2003, page 171 of 196 HD66781 Preliminary 8-color Display Mode The HD66781 incorporates an 8-color display mode. The available grayscale levels are V0 and V63, and the voltages for the other levels (V1-V62) are halted to reduce power consumption. The -fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display mode. Since the power supplies for the levels V1-V62 are halted in the 8-color mode, data are converted to automatically select V0/V63 levels: the MSB of each R, G, B, pixel of GRAM data is allocated to the lower 5 bits of R, G, B of display data. The HD 66781 enables to switch between 8-color and normal display modes without rewriting GRAM data only with the COL setting. MSB R5 R4 R3 R2 R1 R0 GRAM LSB B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 COL[1:0]=h'2 Display data + polar register PKP0[2:0] PKP1[2:0] PKP2[2:0] PKP3[2:0] PKP4[2:0] PKP5[2:0] PRP0[2:0] PRP1[2:0] VRP0[3:0] VRP1[4:0] - polar register PKN0[2:0] PKN1[2:0] PKN2[2:0] PKN3[2:0] PKN4[2:0] PKN5[2:0] PRN0[2:0] PRN1[2:0] VRN0[3:0] VRN1[4:0] R5 R5 R5 R5 R5 R5 G5 G5 G5 G5 G5 G5 B5 B5 B5 B5 B5 B5 V0 6 2 2 gray- scale control 6 2 gray- scale control 6 2 gray- scale control Gray-scale amp 8 LCD driver LCD driver LCD driver RGB LCD LCD Rev.0.5, July.31.2003, page 172 of 196 HD66781 Preliminary Oscillation Circuit The HD66781 generates oscillation by an internal R-C oscillator with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency varies depending on the value of external resistor, the distance of wiring, and the operational power supply voltage. For example, the oscillation frequency becomes low when increasing the value of Rf resistor, or lowering the power supply voltage. See the "Notes to Electric Characteristics" section for the relationship between the Rf resistor value and the oscillation frequency. OSC1 Rf OSC2 HD66781 External Resistor Oscillation Mode Note 1) Place the Rf resistor as close to the OSC1, OSC2 pins as possible. Note 2) Make sure not to arrange other wiring close to or beneath OSC1-OSC2 wiring to avoid effects from coupling Rev.0.5, July.31.2003, page 173 of 196 HD66781 Preliminary n-raster-row Inversion alternating Drive The HD66781, in addition to LCD inversion alternating drive by frame, supports n-raster-row inversion alternating drive where alternation occurs by n raster-rows, where n takes a number from 1 to 64. The nraster-row inversion alternating drive enables to overcome the problems related to display quality. In determining n (the value set by the NW bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal panel. Setting a small number of raster-rows will raise the alternating frequency of the liquid crystal and increase the charge/discharge current on the liquid crystal cells. 1 frame Back porch 1 2 3 4 321 322 Front porch Back porch 1 2 3 4 321 322 1 frame Front porch 336 336 Frame alternating drive -320 raster-rows N-raster-row alternating drive -320 raster-row drive -3 raster-row inversion -EOR = 1 n-raster-row alternating drive Note 1) Make sure to set EOR = 1 to avoid direct bias on liquid crystal during n-raster-row alternating drive. Rev.0.5, July.31.2003, page 174 of 196 HD66781 Preliminary Interlaced Drive The HD66781 supports interlaced drive, which divides one frame into n fields and then drives to prevent flickers. To determine the number of fields (n: value set by the FLD bits), check the display quality on the actual liquid crystal panel. The following table shows the gate selection for each number of fields, 1 to 3. The figure illustrates the output waveforms of the 3-field interlaced drive. Table 75 GA=0, SM=0, GS0=0, GS1=0 GA=1, SM=0, GS0=0, GS1=1 FLD1-0 2'h1 2'h3 FLD1-0 2'h1 2'h3 Field 1 2 3 Field 1 2 3 Gate Gate G1 O O G328 O O G2 O O G327 O O G3 O O G326 O O G4 O O G325 O O G5 O O G324 O O G6 O O G323 O O G7 O O G322 O O G8 O O G321 O O G9 O O G320 O O * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * G317 O O G12 O O G318 O O G11 O O G319 O O G10 O O G320 O O G9 O O Note 1) Interlaced drive is not available in RGB interface mode. Note 2) Middle porch must be set to BP = 3 (3 lines) for interlaced drive. Note 3) OSD ( blending), scrolling, and resizing functions are not available with interlaced drive. Rev.0.5, July.31.2003, page 175 of 196 HD66781 1 frame Blank period Preliminary Field 1 Alternation Polarity G1 G2 G3 G4 G5 G6 Field 2 Field 3 Field 1 G3n+1 G3n+2 G3n+3 3-field interlaced drive: gate output timing Rev.0.5, July.31.2003, page 176 of 196 HD66781 Preliminary Alternating Timing The following figure illustrates the alternating timing of each alternating drive formula. In case of frame inversion alternating drive, alternation occurs at the completion of one frame, followed by a blank that lasts for 16H periods. In case of interlaced drive, alternation occurs at the completion of one field, followed by a blank. The total period of the blanks in one frame adds up to 16H period. In case of n-raster-row, a blank lasting 16H period is inserted after all screens are drawn. During interlaced drive, make the numbers of back, front porches more than the numbers of fields. Frame inversion Alternating drive 3-field interlaced drive n-raster-row inversion Alternating drive Alternating timing Back porch Frame 1 Alternating timing Alternating timing Field 1 Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Alternating timing Blank period 3 Blank period = front porch + back porch Blank period = front porch + back porch Back porch n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows One frame period Alternating timing Field 2 Alternating timing Front porch Blank period 2 Field 3 Alternating timing One frame period Blank period 1 Front porch Alternating timing Rev.0.5, July.31.2003, page 177 of 196 One frame period HD66781 Preliminary Frame-Frequency Adjustment Function The HD66781 incorporates frame frequency adjustment function. The frame frequency during the liquid crystal drive is adjusted by the instruction setting (DIVI, RTNI) while keeping the oscillation frequency fixed. By setting the oscillation frequency high in advance, it becomes possible to switch the frame frequency in accordance to the kind of displayed picture (i.e. moving/still picture). When displaying a still picture, set the frame frequency low to save power consumption, while setting the frame frequency high when displaying a moving picture which requires high-speed screen switching. Relationship between Liquid Crystal Drive Duty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated by the following formula. The frame frequency is adjusted by the instruction setting with the 1-H period adjustment bit (RTNI bit) and the operation clock division bit (DIVI bit). (Formula for the frame frequency) fosc Frame frequency = Clock cycles per raster-row x division ratio x (Line+BP+ FP) : R-C oscillation frequency : RTNI bits : DIVI bit : number of drive raster-rows (NL) : FP bits : BP bits [Hz] fosc Clock cycles per raster-row Division ratio Line Front Porch Back Porch Calculation Example The maximum frame frequency = 60 Hz : 320 : 16 clock cycles (RTNI[4:0] = 2'h10) : 1 division Number of drive raster-row 1-H period Operation clock division ratio fosc = 60 Hz x 16 clocks x 1 division x (320+2+14) lines = 323 (kHz) In this case, the R-C oscillation frequency becomes 323 kHz. Adjust the value of external resistor for R-C oscillator to set the frequency 323kHz. Rev.0.5, July.31.2003, page 178 of 196 HD66781 Preliminary Partial Display Function The HD66781 enables arbitrary settings for on-display picture RAM area and the display position on the screen with the use of OSD. When the display of base image is turned off (BASEE=0), OSD is displayed 100%. By making settings for OSD RAM area (OSA, OEA) and OSD position (ODP), the HD66781 allows displaying an arbitrary set of data. Other than OSD area becomes no-display area to reduce power consumption. The partial display area using OSD can be made up to 3 areas. In combination with 8-color mode and off-scan settings (PTS, PTG, ISC), more power-saving display will be obtained. Make an appropriate setting taking power-saving effect and display quality into consideration. Non-display area G41 First OSD image : 19 raster-rows G59 Non-display area Number of driving raster-row Base picture display ENABLE First OSD picture display RAM area First OSD picture display position First OSD picture display ENABLE : NL0 =6'h07 (64 raster-rows) : BASEE = 0 : (OSA0, OEA0) = (8'h000, 8'h013) : ODP0=8'h028 : OSDE=1 Partial Display Note 1) See the "RAM Address and Display Position on the Panel" for more details on the relationship between the display area and the setting of RAM area. Rev.0.5, July.31.2003, page 179 of 196 HD66781 Preliminary Power-saving drive settings The HD66781 incorporates various settings for lower power consumption display. The low power consumption and the quality of display are in trade-off, and the power-saving effect may vary depending on the characteristics of a panel. Make an appropriate setting among the settings listed below taking the tradeoff into consideration. 1. 8-color display mode (COL) When this mode is selected (COL [1:0] = 2'h2), voltage generation for grayscale levels other than V0 and V63 levels is halted. In this mode, only 8 colors are available for display for saving power. 2. Low power consumption display mode (COL, FRC) Setting COL[1:0] to 2'h1 halts 32 amplifiers among V0 ~ V63 grayscale amplifiers to display with low power consumption. In combination with the FRC mode setting, it is possible to realize display with low power consumption in abundant colors. In this mode, 250,047 colors are available with 18-bit, 16-bit x2, 9-bit x2, 8-bit x3 (RGB 6 bits each) interfaces and 64,512 colors are available with 16-bit x1, 8-bit x2 interfaces and SPI (R, B: 5 bits, G: 6 bits). Using this mode with short screen refreshing cycle may affect the quality of display. Consider the trade-off between the display quality and power-saving effects before use. See the "Low power consumption display mode" (p.169) for details. 3. Partial display (OSD) The partial display is made with OSD and base image display off setting (BASEE = 0). Display operation is limited to the partial display area to save power. Power saving effects will increase as the number of partial display lines decreases. Also, see "Partial Display Function"(p.139) for details. 4. Non-lit drive setting The non-lit drive setting is available for partial display and allows specifying the kind of source outputs in the non-lit drive area with PTS bits. Also, in the non-lit drive area, grayscale generation amplifier is halted and step-up clock cycle is slowed down to half. PTG bits can specify the scan mode of gate bus lines in the non-lit drive area. In the interval gate scan mode, gate bus lines are scanned by the frame cycle specified by ISC bits to hold power consumption required for scanning gate bus lines to minimum. The longer scan cycle may affect the quality of display. Make an appropriate setting by taking trade-off between power-saving effects and display quality. Rev.0.5, July.31.2003, page 180 of 196 HD66781 Table 76 Source outputs in non-display area Source output in non-display area Positive polarity Negative polarity Preliminary PTS[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Non-display area Grayscale amp operation Non-display area Step-up clock frequency V63 Setting disabled GND Hi-Z V63 Setting disabled GND Hi-Z V0 Setting disabled GND Hi-Z V0 Setting disabled GND Hi-Z V0 to V63 V0 to V63 V0 to V63 V0,V63 V0,V63 V0,V63 DC0,DC1Setting DC0,DC1Setting DC0,DC1Setting DC0,DC1Setting x1/2 DC0,DC1Setting x1/2 DC0,DC1Setting x1/2 Note 1) Gate outputs in non-lit drive area can be controlled by off-scan mode (with PTG bits). Note 2) The operation halt of grayscale amplifier and the slowdown of step-up clock frequency are valid only to the non-display area. Note 3) When DC[4:3]=2'h3, the frequency of step-up clocks in the non-display area are not slowed down half even if PTS[2:0] is set to 4, 6 or 7. Table 77 Gate outputs in non-display area PTG[1:0] DISPTMG output Gate output in nonSource output in nondisplay area display area 2'h0 Normal drive Normal scan PTS setting 2'h1 GND DISPTMG (Fixed) PTS setting 2'h2 Internal drive Interval scan PTS setting 2'h3 Setting disabled Note 1) When the interval scan is executed, make setting for the frame alternating drive. Table 78 Interval gate scan frequency ISC[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Scan frequency Setting disabled 3 frames 5 frames 7 frames 9 frames 11 frames 13 frames 15 frames 17 frames 19 frames 21 frames 23 frames 25 frames 27 frames 29 frames 31 frames When (fFLM) = 60Hz - 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms 518ms Rev.0.5, July.31.2003, page 181 of 196 HD66781 5. Frame frequency setting Preliminary Frame frequency adjusting functions (with DIVI, RTNI bits) allows changing liquid crystal alternating frequency through instructions. Frame frequency can be reduced to achieve low power consumption while display method with low power consumption such as partial display mode is employed. See "Frame Frequency Adjustment Function"(p.178) section for details. Generally, the lower frame frequency and the quality of display are in trade-off. The power-saving effects and the quality of display also vary depending on the characteristics of a panel. Check the quality of display on the panel before use. 6. Liquid crystal alternating drive The HD66781 allows selecting among frame alternating drive, 3-field interlace drive, and line inversion alternating drive through instructions (B/C, EOR, NW, and FLD). Select an appropriate alternating drive method for the kind of display. See the "Alternating Timing"(p.177) section for details. Generally, the lower frame frequency and the quality of display are in trade-off. The power-saving effects and the quality of display also vary depending on the characteristics of a panel. Check the quality of display on the panel before use. Rev.0.5, July.31.2003, page 182 of 196 HD66781 Preliminary Equalization function The HD66781 incorporates source-Vcom equalization function, which short-circuits source outputs S1S720 and Vcom at alternating points to equalize the electric potential of source capacities and Vcom capacities during "High" period of EQ signal. By driving source and Vcom from the equalized electric potential, the electric charges accumulated in the source and Vcom capacities are reallocated, and power consumption is reduced. Normal Display Equalization + + + + + + S1 S720 S1 S720 EQ EQ EQ EQ EQ EQ EQ EQ VCOM VCOM HD66781 HD66781 EQ VCOM EQ VCOM HD66783/HD667P21 HD66781/HD667P21 Note 1) Equalization function is only available when Vcom Low level 0V Note 2) Power-saving effects depend on display data. Rev.0.5, July.31.2003, page 183 of 196 HD66781 Preliminary Specifications of external element of HD66781 The specifications of external element connected to power supply circuit of HD66781 are as follows. Table 79 Capacitor Recommended capacitor voltage 3V Capacitor capacitance 1F Characteristics B Connection pin VDD Rev.0.5, July.31.2003, page 184 of 196 HD66781 Preliminary Instruction Setting The following flowcharts show the sequences with respect to power on/off of the combined use of HD66781 and HD66783 or HD667P21, display on/off, standby set/release, and sleep set/release. Whenever turning on or off the power supply and so on, it must be done in accordance to the following procedures. A serial interface is used to make instruction settings to the HD66783 and HD667P21, where a serial transfer is always required. The serial transfer must be made in accordance to the serial transfer sequence and right after the instructions are set. Timing of the instruction setting is necessary to take into consideration the delay of 16-cycle internal clocks (OSC) from the start of serial transfer from the HD66781 through TE and IDX2-0 before each of the following mode settings becomes effective on the HD66783 and HD667P21. Rev.0.5, July.31.2003, page 185 of 196 HD66781 Power-supply/display ON (LPTS = 0: a-Si TFT panel, with HD66783) Display ON Instructions before power supply startup SAP setting (HD6678) Preliminary Power supply ON Sequence Power supply ON (Vcc, IOVcc, Vcc1, Vci) The power-suppy must be turned on in the order of IOVcc, Vcc1(781), Vcc(783), Vcc(781), Vci or all power-supplies must be turned on simultaneously. Power ON reset 1ms or more VDD startup oscillation start 2 frames or more Display ON (1) D1-0 = 2'h1 Instructions before power supply startup Power-supply control register setting (HD66783) VC, VRH, (PON = 0) settings serial transfer VCM, VDV, DC1=3'h0 settings serial transfer DK = 1 setting serial transfer Display ON (2) GON="1" serial transfer Display ON (3) D1-0 = 2'h3 2 frames or more Instructions for starting up power supply(1) sPower-supply operation start settings (HD66781) AP setting (HD66783) AP, DC0, BT (VCOMG = 0, GON = 0) settings serial transfer DC1 settings serial transfer PON = 1 setting see Note 2) serial transfer 30ms or more VGH, VGL start up Display ON (4) DTE ="1" Display ON Display each image by setting BASEE and OSDE to 1 (Display ENABLE). Instructions for starting Power supply(2) 100ms or more Power-supply operation start setting VCOMG = 1 serial transfer DK = 0 setting serial transfer DDVDH, VCL start up 70ms or more Note 1) Do not set GON = 1 while D - 2'h0. Note 2) AP[2:0] setting must be compleged before or simultaneously with setting PON = 1. While PON = 1, no change to the AP[2:0] setting will be accepted except AP[2:0] = 3'h0 while the power supply is turned off. Instructions for other mode settings Serial transfer Display control register settings NL, GS, SCN settings serial transfer other settings GRAM write Display ON flow Rev.0.5, July.31.2003, page 186 of 196 HD66781 Power-supply/display OFF (LPTS = 0: a-Si TFT panel, with HD66783) Display OFF Preliminary Power supply OFF Sequence ( 2 frames or more EQW =0 ) required only when equalization function is in use. Instructions for setting power supply OFF Power-supply off setting bits (HD66781) SAP = 3'h0, AP = 3'h0 (HD66783) VCOMG =0, AP = 3'h0 serial transfer PON =0 see Note 2) serial transfer Display OFF (1) D1-0 = "2'h2" Display OFF (2) DTE = 0 Display OFF (3) GON = 0 Serial transfer Power supply OFF (Vcc, Vci, IOVcc,Vcc1) The power-suppy must be turned on in the order of Vcc(781), Vci, IOVcc, Vcc1, Vcc(783) or all power-supplies must be turned on simultaneously. Display OFF (4) D1-0="2'h0" Note 1) Do not set GON = 1 when D=2'h0 Note 2) Set PON = 0 after transferring the AP[2:0] = 3'h0 setting to HD66783 when the power-supply is turned off. Rev.0.5, July.31.2003, page 187 of 196 HD66781 Power-supply/display ON (LPTS = 1: LTPS TFT panel, with HD667P21) Display ON Instructions before power supply startup SAP setting (HD6678) Gate driver/LTPS LCD panel control signal register settings LPTS = 1 FW, FT settings SW, ST settings DPW, DPT settings SDT setting Preliminary Power supply ON Sequence Power supply ON (Vcc, IOVcc, Vcc1, Vci) The power-suppy must be turned on in the order of IOVcc, Vcc1(781), Vcc(7P21), Vcc(781), Vci or all power-supplies must be turned on simultaneously. Power ON reset 1ms or more VDD startup oscillation start Instructions before power supply startup Power-supply control register settings (HD667P21) VC, VRH, (PON = 0) settings serial transfer VCM, VDVsettings serial transfer VGH, VGL settings serial transfer DK[1:0] = 2'h1 setting serial transfer 2 frames or more Display ON (1) D1-0 = 2'h1 Display ON (2) GON="1" serial transfer Display ON (3) D1-0 = 2'h3 2 frames or more Instructions for starting up power supply(1) Power-supply operation start setting (HD66781) AP setting (HD667P21) AP, DC, BT settings (VCOMG = 0, GON = 0) setting serial transfer PON = 1 setting serial transfer 30ms or more VLOUT2, VLOUT3 start up Display ON (4) DTE ="1" Display ON Display each image by setting BASEE and OSDE to 1 (Display ENABLE). Instructions for starting Power supply(2) Power-supply operation start setting (HD667P21) DK = 2'h0 setting see Note 2) serial transfer 20ms or more VLOUT1 start up Instructions for starting Power supply(3) Power-supply operation start setting VCOMG = 1 serial transfer 60ms or more VLOUT4 start up step-up circuits stabilizing time Note 1) Do not set GON = 1 while D - 2'h0. Note 2) Start up VLOUT1 after waiting VLOUT2 to start up completely so that it is always VLOUT 2>VLOUT1. When using 4-time stepped-up VLOUT2, first start up VLOUT2 to step up 5 times, and then resetting VLOUT2 to step up 4 times after starting up VLOUT1. Instructions for other mode settings Serial transfer GRAM write Display ON flow Rev.0.5, July.31.2003, page 188 of 196 HD66781 Power-supply/display OFF (LPTS = 1: LPTS TFT panel, with HD667P21) Display OFF Preliminary Power supply OFF Sequence ( 2 frames or more EQW =0 ) required only when equalization function is in use. Instructions for setting power supply OFF Power-supply off setting bits (HD66781) SAP = 3'h0, AP = 3'h0 (HD667P21) VCOMG =0, AP = 3'h0 serial transfer PON =0 serial transfer Display OFF (1) D1-0 = "2'h2" Display OFF (2) DTE = 0 2 frames or more Display OFF (3) GON = 0 Serial transfer Power supply OFF (Vcc, Vci, IOVcc,Vcc1) The power-suppy must be turned on in the order of Vcc(781), Vci, IOVcc, Vcc1, Vcc(7P21) or all power-supplies must be turned on simultaneously. Display OFF (4) D1-0="2'h0" Note: Do not set GON = 1 whenever D=2'h0 Rev.0.5, July.31.2003, page 189 of 196 HD66781 Standby/Sleep mode Standby Sleep Preliminary Display OFF sequence Standby Set Display OFF sequence Power-supply OFF sequence Sleep set (SLP="1") Power-supply OFF sequence Standby set (STB="1") Sleep set Oscillation start 1ms or more Standby release Sleep release (SLP="0") wait 1 clock see Note Standby release (STB="0") Sleep release Power supply ON sequence Power supply ON sequence Display ON sequence Display ON sequence Note: The clock refers to internal clock OSC1. Rev.0.5, July.31.2003, page 190 of 196 HD66781 Deep standby mode Deep standby mode Display OFF flow Preliminary Power-supply OFF flow Set Deep standby Set Deep standby DSTB="1" Deep standby mode CS="Low" (1) CS="Low" (2) 1ms or more VDD startup oscillation stabilization period CS="Low" (3) CS="Low" (4) CS="Low" (5) CS="Low" (6) internal initialization Release Deep standby input CS="Low" x 6 Power-supply setting Display ON flow Note 1) See AC characteristics of each interface mode in "Electrical Characteristics" with regard to Low width (PWLW), High width (PWHW) and cycle (tCYCW) periods. Note 2) Leave at least 1ms between 2nd and 3rd inputs of CS="Low". Rev.0.5, July.31.2003, page 191 of 196 HD66781 Low power consumption display mode Preliminary 262,144 color mode to Low power consumption display mode 262,144-color mode display Low power consumption display mode to 262,144 color mode Low power consumption display mode FRCON=1 (D16B = 1) FRCON=0 COL=2'h1 COL=2'h0 1frame at max. 1frame at max. Low power consumption display mode 262,144-color mode display 8-color mode 262,144 color mode to 8-color mode 262,144-color mode display 8-color mode to 262,144 color mode 8-color mode display CL=2'h2 CL=2'h0 1frame at max. 1frame at max. 262,144-color mode display 8-color mode display Rev.0.5, July.31.2003, page 192 of 196 HD66781 Partial display mode Preliminary Full-screen display OSD display setting OSA,OEA,ODP Base image display OFF BASEE=0 OSD display ON OSDE=1 Non-display area drive settings: PTS, PTG, ISC As required 8-color mode setting: COL = 2'h2 Partial display ON Base image display ON BASEE=1 OSD display OFF OSDE=0 Full-screen display Rev.0.5, July.31.2003, page 193 of 196 HD66781 Preliminary Absolute Maximum Values Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Input voltage Operating temperature Symbol IOVcc, Vcc1 Vcc - GND DDVDH - GND Vt Topr Unit V V V V C Value -0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 6.5 -0.3 ~ Vcc + 0.3 -40 ~ + 85 Notes 1, 2, 5 1, 3, 5 1, 4 1 1, 6 Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above absolute maximum values. It is also recommended to use the LSI within the limit of its electric characteristics during normal operation. Exceeding the conditions may lead to malfunction of LSI and affect its credibility. Note 2) IOVcc(High) GND(Low), Vcc1(High) GND(Low) must be observed. Note 3) Vcc(High) GND(Low) must be observed. Note 4) DDVDH(High) GND(Low) must be observed. Note 5) Vcc(High) IOVcc(Low), Vcc(High) Vcc1(Low) must be observed. Note 6) The DC and AC characteristics of chip and wafer products are guaranteed at 85 C. Note 7) The electric potential of this LSI's substrate is GND. The electrical connection of the other side of the chip must be at the electric potential of an insulated state or GND. The electrical and operational characteristics of the LSI will not be guaranteed otherwise. Rev.0.5, July.31.2003, page 194 of 196 HD66781 Preliminary Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.0.5, July.31.2003, page 195 of 196 HD66781 Preliminary Revision Record Rev. 0.5 Date Contents of Modification Drawn by Approved by 2003, July 31 First issue Rev.0.5, July.31.2003, page 196 of 196 |
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